WM8952ECSSLASHRV datasheet(46/72 Pages) WOLFSON

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WM8952

Pre Production

PP, Rev 3.1, June 2011

EXAMPLE:

PLL input clock (f1) is 12MHz and the required clock (SYSCLK) is 12.288MHz.

R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable

divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.

Enabling the divide by 2 sets the required f2 = 4 * 2 * 12.288MHz = 98.304MHz.

R = 98.304 / 12 = 8.192

N = int R = 8

K = int (224 x (8.192 – 8)) = 3221225 = 3126E9h

So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.

The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings

are shown in Table 35.

MCLK

(MHz)

DESIRED

OUTPUT

(MHz)

PRESCALE

DIVIDE

POSTSCALE

DIVIDE

(MCLKDIV)

(Hex)

11.2896

90.3168

7.5264

86C226

12.2880

98.3040

8.192

3126E9

11.2896

90.3168

6.947446

F28BD4

12.2880

98.3040

7.561846

8FD525

14.4

11.2896

90.3168

6.272

45A1CA

14.4

12.2880

98.3040

6.826667

D3A06E

19.2

11.2896

90.3168

9.408

6872B0

19.2

12.2880

98.3040

10.24

3D70A3

19.68

11.2896

90.3168

9.178537

2DB492

19.68

12.2880

98.3040

9.990243

FD809F

19.8

11.2896

90.3168

9.122909

1F76F8

19.8

12.2880

98.3040

9.929697

EE009E

11.2896

90.3168

7.5264

86C226

12.2880

98.3040

8.192

3126E9

11.2896

90.3168

6.947446

F28BD4

12.2880

98.3040

7.561846

8FD525

11.2896

90.3168

6.690133

BOAC93

12.2880

98.3040

7.281778

482296

Table 35 PLL Frequency Examples

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