Data Sheet

ADF7020

Rev. D | Page 39 of 48

REGISTER 5—SYNC BYTE REGISTER

PL2

0

0

1

1

PL1

0

1

0

1

SYNC BYTE

LENGTH

12 BITS

16 BITS

20 BITS

24 BITS

MT2

0

0

1

1

MT1

0

1

0

1

MATCHING

TOLERANCE

0 ERRORS

1 ERROR

2 ERRORS

3 ERRORS

SYNC BYTE SEQUENCE

CONTROL

BITS

Figure 50. Register 5—Sync Byte Register

Register 5—Sync Byte Register Comments

•

Sync byte detect is enabled by programming Bits R4_DB[25:23] to 010 or 011.

•

This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK

pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine

data bits.

•

The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte

detection hardware.

•

Choose a sync byte pattern that has good autocorrelation properties, for example, 0x123456.