EVAL-ADF7020DBZ2 datasheet(8/48 Pages) AD

Il numero della parte	EVAL-ADF7020DBZ2

Spiegazioni elettronici	High Performance, ISM Band, FSK/ASK Transceiver IC

PDF	48 Pages

Scroll/Zoom	100%

Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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8 / 48 page

ADF7020

Data Sheet

Rev. D | Page 8 of 48

TIMING CHARACTERISTICS

VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, not production tested.

Table 2.

Parameter

Limit at TMIN to TMAX

Unit

Test Conditions/Comments

>10

SDATA to SCLK setup time

>10

SDATA to SCLK hold time

>25

SCLK high duration

>25

SCLK low duration

>10

SCLK to SLE setup time

>20

SLE pulse width

<25

SCLK to SREAD data valid, readback

<25

SREAD hold time after SCLK, readback

t10

>10

SCLK to SLE disable time, readback

TIMING DIAGRAMS

SCLK

SLE

DB31 (MSB)

DB30

DB2

DB1

(CONTROL BIT C2)

SDATA

DB0 (LSB)

(CONTROL BIT C1)

Figure 2. Serial Interface Timing Diagram

t10

RV16

RV15

RV2

RV1

SCLK

SDATA

SLE

SREAD

(CONTROL BIT C1)

R7_DB0

Figure 3. Readback Timing Diagram

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