EVAL-ADF7020DBZ2 datasheet(24/48 Pages) AD

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ADF7020

Data Sheet

Rev. D | Page 24 of 48

Internal AFC

The ADF7020 supports a real-time internal automatic

frequency control loop. In this mode, an internal control

loop automatically monitors the frequency error and adjusts

the synthesizer N divider using an internal PI control loop.

The internal AFC control loop parameters are controlled in

R11_DB20 to 1. A scaling coefficient must also be entered,

based on the crystal frequency in use. This is set up in

Bits R11_DB[4:19] and should be calculated using

AFC_Scaling_Coefficient = (500 × 224)/XTAL

Therefore, using a 10 MHz XTAL yields an AFC scaling

coefficient of 839.

AFC Performance

The improved sensitivity performance of the Rx when AFC is

enabled and in the presence of frequency errors is shown in

Figure 18. The maximum AFC frequency range is ±50 kHz,

which corresponds to ±58 ppm at 868 MHz. This is the total

error tolerance allowed in the link. For example, in a point-to-

point system, AFC can compensate for two ±29 ppm crystals or

one ±50 ppm crystal and one ±8 ppm TCXO.

AFC settling typically takes 48 bits to settle within ±1 kHz. This

can be improved by increasing the postdemodulator bandwidth

in Register 4 at the expense of Rx sensitivity.

When AFC errors have been removed using either the internal

or external AFC, further improvement in the receiver’s sensi-

tivity can be obtained by reducing the IF filter bandwidth using

Bits R1_DB[22:23].

AUTOMATIC SYNC WORD RECOGNITION

The ADF7020 also supports automatic detection of the sync or

ID fields. To activate this mode, the sync (or ID) word must be

preprogrammed into the ADF7020. In receive mode, this

preprogrammed word is compared to the received bit stream

and, when a valid match is identified, the external pin

INT/LOCK is asserted by the ADF7020.

This feature can be used to alert the microprocessor that a valid

channel has been detected. It relaxes the computational require-

ments of the microprocessor and reduces the overall power

consumption. The INT/LOCK is automatically deasserted again

after nine data clock cycles.

The automatic sync/ID word detection feature is enabled by

selecting Demodulator Mode 2 or Demodulator Mode 3 in the

demodulator setup register. Do this by setting Bits R4_DB[25:23] =

010 or 011. Bits R5_DB[4:5] are used to set the length of the

sync/ID word, which can be 12, 16, 20, or 24 bits long. The

transmitter must transmit the MSB of the sync byte first and the

LSB last to ensure proper alignment in the receiver sync byte

detection hardware.

For systems using forward error correction (FEC), an error

tolerance parameter can also be programmed that accepts a

valid match when up to three bits of the word are incorrect. The

error tolerance value is assigned in Bits R5_DB[6:7].

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