EVAL-ADF7020DBZ2 datasheet(7/48 Pages) AD

7 / 48 page

Data Sheet

ADF7020

Rev. D | Page 7 of 48

Parameter

Min

Typ

Max

Unit

Test Conditions

REFERENCE INPUT

Crystal Reference

3.625

MHz

External Oscillator

3.625

MHz

Load Capacitance

See crystal manufacturer’s specification sheet

Crystal Start-Up Time

2.1

11.0592 MHz crystal, using 33 pF load capacitors

1.0

Using 16 pF load capacitors

Input Level

CMOS levels

See the

Reference Input section

ADC PARAMETERS

INL

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

DNL

±1

LSB

From 2.3 V to 3.6 V, TA = 25°C

TIMING INFORMATION

Chip Enabled to Regulator Ready

µs

CREG = 100 nF

Chip Enabled to RSSI Ready

3.0

See

Table 11 for more details

Tx to Rx Turnaround Time

150 µs +

(5 × TBIT)

Time to synchronized data out, includes AGC settling;

see the

AGC Information and Timing section

LOGIC INPUTS

Input High Voltage, VINH

0.7 ×

VDD

Input Low Voltage, VINL

0.2 ×

VDD

Input Current, IINH/IINL

±1

µA

Input Capacitance, CIN

Control Clock Input

MHz

LOGIC OUTPUTS

Output High Voltage, VOH

DVDD −

0.4

IOH = 500 µA

Output Low Voltage, VOL

0.4

IOL = 500 µA

CLKOUT Rise/Fall

CLKOUT Load

TEMPERATURE RANGE, TA

−40

+85

°C

POWER SUPPLIES

Voltage Supply

VDD

2.3

3.6

All VDD pins must be tied together

Transmit Current Consumption

FRF = 915 MHz, VDD = 3.0 V,

PA is matched to 50 Ω

−20 dBm

14.8

Combined PA and LNA matching network as on

EVAL-ADF7020DBZx boards

VCO_BIAS_SETTING = 12

−10 dBm

15.9

0 dBm

19.1

10 dBm

28.5

10 dBm

26.8

PA matched separately with external antenna

switch, VCO_BIAS_SETTING = 12

Receive Current Consumption

Low Current Mode

High Sensitivity Mode

Power-Down Mode

Low Power Sleep Mode

0.1

µA

1 Higher data rates are achievable, depending on local regulations.

2 For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.

3 For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.

4 Measured as maximum unmodulated power. Output power varies with both supply and temperature.

5 For matching details, see the LNA/PA Matching section and the AN-764 Application Note.

6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.

7 See Table 5 for a description of different receiver modes.

8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

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