EVAL-ADF7020DBZ2 datasheet(18/48 Pages) AD

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ADF7020

Data Sheet

Rev. D | Page 18 of 48

TRANSMITTER

RF OUTPUT STAGE

The PA of the ADF7020 is based on a single-ended, controlled

current, open-drain amplifier that has been designed to deliver

up to 13 dBm into a 50 Ω load at a maximum frequency of

956 MHz.

The PA output current and, consequently, the output power are

programmable over a wide range. The PA configurations in

FSK/GFSK and ASK/OOK modulation modes are shown in

Figure 25 and Figure 26, respectively. In FSK/GFSK modulation

mode, the output power is independent of the state of the

DATA I/O pin. In ASK/OOK modulation mode, it is dependent

on the state of the DATA I/O pin and Bit R2_DB29, which

selects the polarity of the TxData input. For each transmission

mode, the output power can be adjusted as follows:



FSK/GFSK

The output power is set using Bits R2_DB[9:14].



ASK

The output power for the inactive state of the TxData input

is set by Bits R2_DB[15:20]. The output power for the

active state of the TxData input is set by Bits R2_DB[9:14].



OOK

The output power for the active state of the TxData input

is set by Bits R2_DB[9:14]. The PA is muted when the TxData

input is inactive.

IDAC

R2_DB[9:14]

R2_DB4

R2_DB5

DIGITAL

LOCK DETECT

R2_DB[30:31]

RFGND

RFOUT

FROM VCO

Figure 25. PA Configuration in FSK/GFSK Mode

IDAC

R2_DB[9:14]

R2_DB[15:23]

R2_DB4

R2_DB5

DIGITAL

LOCK DETECT

R2_DB[30:31]

R2_DB29

RFGND

RFOUT

FROM VCO

ASK/OOK MODE

DATA I/O

Figure 26. PA Configuration in ASK/OOK Mode

The PA is equipped with overvoltage protection, which makes it

robust in severe mismatch conditions. Depending on the applica-

tion, one can design a matching network for the PA to exhibit

optimum efficiency at the desired radiated output power level

for a wide range of different antennas, such as loop or mono-

pole antennas. See the LNA/PA Matching section for details.

PA Bias Currents

Control Bits R2_DB[30:31] facilitate an adjustment of the PA

bias current to further extend the output power control range,

if necessary. If this feature is not required, the default value of

7 μA is recommended. The output stage is powered down by

resetting Bit R2_DB4. To reduce the level of undesired spurious

emissions, the PA can be muted during the PLL lock phase by

toggling this bit.

MODULATION SCHEMES

Frequency Shift Keying (FSK)

Frequency shift keying is implemented by setting the N value

for the center frequency and then toggling this with the TxData

line. The deviation from the center frequency is set using

Bits R2_DB[15:23]. The deviation from the center frequency

in Hz is

]

[

Number

Modulation

PFD

FSK

DEVIATION





where Modulation Number is a number from 1 to 511

(R2_DB[15:23]).

Select FSK using Bits R2_DB[6:8].

VCO

÷N

THIRD-ORDER

Σ-∆ MODULATOR

PFD/

CHARGE

PUMP

INTEGER-N

FRACTIONAL-N

PA STAGE

–

fDEV

TxDATA

FSK DEVIATION

FREQUENCY

Figure 27. FSK Implementation

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