AD9753AST datasheet(6/28 Pages) AD

6 / 28 page

REV. B

–6–

AD9753

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

RESET

Internal Clock Divider Reset

CLK+

Differential Clock Input

CLK–

Differential Clock Input

4, 22

DCOM

Digital Common

5, 21

DVDD

Digital Supply Voltage

PLLLOCK

Phase-Locked Loop Lock Indicator Output

7–18

P1B11–P1B0

Data Bits DB11 to DB0, Port 1

19–20, 35–36

RESERVED

23–34

P2B11–P2B0

Data Bits DB11 to DB0, Port 2

37, 38

DIV0, DIV1

Control Inputs for PLL and Input Port Selector Mode. See Tables I and II for details.

REFIO

Reference Input/Output

FSADJ

Full-Scale Current Output Adjust

AVDD

Analog Supply Voltage

IOUTB

Differential DAC Current Output

IOUTA

Differential DAC Current Output

ACOM

Analog Common

CLKCOM

Clock and Phase-Locked Loop Common

LPF

Phase-Locked Loop Filter

PLLVDD

Phase-Locked Loop Supply Voltage

CLKVDD

Clock Supply Voltage

PIN CONFIGURATION

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD9753

RESERVED

P2B0–LSB

P2B1

P2B2

P2B3

P2B4

P2B5

P2B6

P2B7

P2B8

P2B9

RESET

CLK+

CLK–

DCOM

DVDD

PLLLOCK

MSB–P1B11

P1B10

P1B9

P1B8

P1B7

P1B6

RESERVED = NO

USER CONNECTIONS

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