MX25L6445E datasheet(71/72 Pages) MCNIX

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MX25L6445E

P/N: PM1736

REV. 1.8, DEC. 26, 2011

REVISION HISTORY

Revision No. Description

Page

Date

1.0

1. Removed "Preliminary"

MAY/19/2009

2. Merge MX25L6445E and MX25L12845E together

All

3. Add CFI mode content

P37

4. Align waveform format

All

5. Modify tCH/tCL value, from rev0.06 tCH/tCL=5.5ns

P43,45

to rev1.0 tCH/tCL(FAST_READ/READ)=4.5/9ns

6. Change command table format

P15,16

7. Added "DATA RETENTION" Condition

P66

8. Modified sector erase time from 90ms to 60ms

P5,43,46,

P66

9. Modified 128Mb chip erase time (max) from 512s to 200s

P46,66

1.1

1. Added 128M 8-WSON EPN

P67

JUL/16/2009

2. Change RDCFI command from A5 to 5A

P16,37

1.2

1. Added DMC Code content table

P37~39

OCT/21/2009

2. Removed MX25L12845EZNI-10G advanced information remark

P69

3. Changed the naming "CFI mode" as "DMC mode"

All

1.3

1. Corrected error

P8,43,44,54 APR/01/2010

P68

2. Added wording "e.g. Vcc and CS# ramp up simultaneously"

P67

3. Modified low active read and standby current consumption

P5,43~44,69

and deep power down current consumption

4. Deleted parallel mode condition

P43

5. Modified table of "Read DMC mode (RDDMC)"

P37~39

6. Added "Input Test Waveforms And Measurement Level"

P42

7. Modified tSLCH, tSHCH from 8ns to 5ns

P45,47

1.4

1. Removed DMC sequence description & content table

P6,14,16,37 JUL/14/2010

2. Revised low active read current spec

3. Revised Table 7-1 and Table 7-2

P40-41

1.5

1. Removed MX25L12845E information from the previous combined

All

AUG/19/2011

version of MX25L6445E/MX25L12845E

2. Modified description for RoHS compliance

P6,60,61

3. Revised Figure 18. Fast DT Read (FASTDTRD) Sequence

P46,47,49

Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence;

Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence; and

Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance.

4. Corrected ILO TEST CONDITIONS in Table 7

P39

5. Revised Storage Temperature

P37

1.6

1. Changed Quad I/O Read Frequency from 80MHz@VCC=3.0V~3.6V P40

SEP/13/2011

to 85MHz@VCC=3.0V~3.6V

1.7

1. Revised the description in The individual block lock mode

P31

OCT/05/2011

1.8

1. Modified Input Capacitance

P43

DEC/26/2011

2. Modified Figure 41. Power-Down Sequence

P64

3. Added Read SFDP (RDSFDP) Mode

P6,13,14,

P36~41

4. Changed ordering information format

P66

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