MX25L6445E datasheet(21/72 Pages) MCNIX

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MX25L6445E

P/N: PM1736

REV. 1.8, DEC. 26, 2011

P[7:0]→ 4 dummy cycles → data out still CS# goes high → CS# goes low (reduce 4Read instruction) → 24-bit ran-

dom access address (Please refer to Figure 22 for 4x I/O Read Enhance Performance Mode timing waveform).

In the performance-enhancing mode (Notes of Figure. 22), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h,

5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer

toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h. These commands will reset the performance enhance

mode. And afterwards CS# is raised and then lowered, the system then will return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(12) 4 x I/O Double Transfer Rate Read Mode (4DTRD)

The 4DTRD instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad

Enable (QE) bit of status Register must be set to "1" before sending the 4DTRD instruction. The address (interleave

on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on

both rising and falling edge of SCLK at a maximum frequency fQ2. The 8-bit address can be latched-in at one clock,

and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall-

ing edge of clock. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single 4DTRD instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 4DTRD instruc-

tion, the following address/dummy/data out will perform as 8-bit instead of previous 1-bit.

The sequence of issuing 4DTRD instruction is: CS# goes low → sending 4DTRD instruction (1-bit per clock) → 24-

bit address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → 8 dummy clocks → data out interleave on

SIO3, SIO2, SIO1 & SIO0 (8-bit per clock) → to end 4DTRD operation can use CS# to high at any time during data

out (Please refer to Figure 23 for 4 x I/O Read Mode Double Transfer Rate Timing Waveform).

Another sequence of issuing enhanced mode of 4DTRD instruction especially useful in random access is: CS# goes

low → sending 4DTRD instruction (1-bit per clock) → 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 (8-bit

per clock) → performance enhance toggling bit P[7:0] → 7 dummy clocks → data out(8-bit per clock) still CS#

goes high → CS# goes low (eliminate 4 Read instruction) → 24-bit random access address (Please refer to Figure

24 for 4x I/O Double Transfer Rate read enhance performance mode timing waveform).

While Program/Erase/Write Status Register cycle is in progress, 4DTRD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

(13) Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for

any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before

sending the Sector Erase (SE). Any address of the sector (see Table 4) is a valid address for Sector Erase (SE) in-

struction. The CS# must go high exactly at the byte boundary (the least significant bit of the address been latched-

in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI

→CS# goes high. (Please refer to Figure 25)

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

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