MX25L6445E datasheet(30/72 Pages) MCNIX

30 / 72 page

MX25L6445E

P/N: PM1736

REV. 1.8, DEC. 26, 2011

(27) Write Protection Selection (WPSEL)

There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,

flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value

of WPSEL is “0”. WPSEL command can be used to set WPSEL=1.

Please note that WPSEL is an OTP bit. Once

WPSEL is set to 1, there is no chance to recovery WPSEL back to “0”. If the flash is put on BP mode, the indi-

vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode

is disabled.

Every time after the system is powered-on the Security Register bit 7 is checked. If WPSEL=1, all the blocks

and sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and

GBULK instructions. Program or erase functions can only be operated after the Unlock instruction is executed.

BP protection mode, WPSEL=0:

ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7

of status register that can be set by WRSR command.

Individual block protection mode, WPSEL=1:

Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK

command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, bit 7 in

the security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct

block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-

ods. Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.

Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.

The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual

block protect mode → CS# goes high.

WPSEL instruction function flow is as follows:

64KB

BP3 BP2 BP1 BP0

SRWD

WP# pin

BP and SRWD if WPSEL=0

(1) BP3~BP0 is used to define the protection group region.

(The protected area size see Table 2)

(2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this

case, SRWD and BP3~BP0 of status register bits can not

be changed by WRSR

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