MX25L6445E datasheet(3/72 Pages) MCNIX

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MX25L6445E

P/N: PM1736

REV. 1.8, DEC. 26, 2011

(25) Read Security Register (RDSCUR) .......................................................................................................... 28

Security Register Definition.............................................................................................................................. 29

(26) Write Security Register (WRSCUR).......................................................................................................... 29

(27) Write Protection Selection (WPSEL)......................................................................................................... 30

BP and SRWD if WPSEL=0 ............................................................................................................................. 30

The individual block lock mode is effective after setting WPSEL=1................................................................. 31

WPSEL Flow .................................................................................................................................................... 32

(28) Single Block Lock/Unlock Protection (SBLK/SBULK)............................................................................... 33

Block Lock Flow ............................................................................................................................................... 33

Block Unlock Flow............................................................................................................................................ 34

(29) Read Block Lock Status (RDBLOCK)....................................................................................................... 35

(30) Gang Block Lock/Unlock (GBLK/GBULK)................................................................................................. 35

(31) Clear SR Fail Flags (CLSR)...................................................................................................................... 35

(32) Enable SO to Output RY/BY# (ESRY)...................................................................................................... 35

(33) Disable SO to Output RY/BY# (DSRY)..................................................................................................... 35

(34) Read SFDP Mode (RDSFDP)................................................................................................................... 36

POWER-ON STATE ...................................................................................................................................................42

ELECTRICAL SPECIFICATIONS..............................................................................................................................43

ABSOLUTE MAXIMUM RATINGS................................................................................................................... 43

Figure 2. Maximum Negative Overshoot Waveform ........................................................................................ 43

CAPACITANCE TA = 25°C, f = 1.0 MHz........................................................................................................... 43

Figure 3. Maximum Positive Overshoot Waveform .......................................................................................... 43

Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................ 44

Figure 5. OUTPUT LOADING ......................................................................................................................... 44

Table 10. DC CHARACTERISTICS ................................................................................................................. 45

Table 11. AC CHARACTERISTICS .................................................................................................................. 46

Timing Analysis ........................................................................................................................................................48

Figure 6. Serial Input Timing ............................................................................................................................ 48

Figure 7. Output Timing.................................................................................................................................... 48

Figure 8. Serial Input Timing for Double Transfer Rate Mode.......................................................................... 49

Figure 9. Serial Output Timing for Double Transfer Rate Mode ....................................................................... 49

Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1............................................... 50

Figure 11. Write Enable (WREN) Sequence (Command 06) ........................................................................... 50

Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................ 50

Figure 13. Read Identification (RDID) Sequence (Command 9F).................................................................... 51

Figure 14. Read Status Register (RDSR) Sequence (Command 05) .............................................................. 51

Figure 15. Write Status Register (WRSR) Sequence (Command 01)............................................................. 51

Figure 16. Read Data Bytes (READ) Sequence (Command 03) .................................................................... 52

Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) ................................................ 52

Figure 18. Fast DT Read (FASTDTRD) Sequence (Command 0D)................................................................. 52

Figure 19. 2 x I/O Read Mode Sequence (Command BB)............................................................................... 53

Figure 20. Fast Dual I/O DT Read (2DTRD) Sequence (Command BD)......................................................... 53

Figure 21. 4 x I/O Read Mode Sequence (Command EB)............................................................................... 54

Figure 22. 4 x I/O Read Enhance Performance Mode Sequence (Command EB) .......................................... 54

Figure 23. Fast Quad I/O DT Read (4DTRD) Sequence (Command ED)........................................................ 55

Figure 24. Fast Quad I/O DT Read (4DTRD) Enhance Performance Sequence (Command ED)................... 55

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