AS5047D datasheet(10/37 Pages) AMSCO

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AS5047D – 10

ams Datasheet: 2014-Jun-27 [v1-02]

De tail ed De sc rip t ion

After applying power to the chip, the power-on time (tpon) must

elapse before the AS5047D provides the first valid data.

Dynamic Angle Error Compensation

The AS5047D uses 4 integrated Hall sensors which produce a

voltage proportional to the orthogonal component of the

magnetic field to the die. These voltage signals are amplified,

filtered, and converted into the digital domain to allow the

CORDIC digital block to calculate the angle of the magnetic

vector. Propagation of these signals through the analog

front-end and digital back-end generates a fixed delay between

the time of measurement and the availability of the measured

angle at the outputs. This latency generates a dynamic angle

error represented by the product of the angular speed (

ω)and

the system propagation delay (tdelay):

DAE =

ω x tdelay

The dynamic angle compensation block calculates the current

magnet rotation speed (

ω) and multiplies it with the system

propagation delay (tdelay) to determine the correction angle to

reduce this error. At constant speed, the residual system

propagation delay is tdelay_DAEC.

The angle represented on the PWM interface is not

compensated by the Dynamic Angle Error Compensation

algorithm. it is also possible to disable the Dynamic Angle Error

Compensation with the setting DAECDIS. Disabling the

Dynamic Angle Error Compensation gives a noise benefit of

0.016 degree rms.This setting can be advantageous for low

speed (under 100rpm) respectively static positioning

applications.

SPI Interface (slave)

The SPI interface is used by a host microcontroller (master) to

read or write the volatile memory as well as to program the

non-volatile OTP registers. The AS5047D SPI only supports slave

operation mode. It communicates at clock rates up to 10 MHz.

The AS5047D SPI uses mode=1 (CPOL=0, CPHA=1) to exchange

data. As shown in Figure 11, a data transfer starts with the

falling edge of CSn (SCL is low). The AS5047D samples MOSI

data on the falling edge of SCL. SPI commands are executed at

the end of the frame (rising edge of CSn). The bit order is MSB

first. Data is protected by parity.

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