MX25R8035F datasheet(14/89 Pages) MCNIX

14 / 89 page

ADVANCED INFORMATION

REV. 0.01, JAN. 06, 2015

MX25R8035F

P/N: PM2164

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended

operation.

2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until

next CS# falling edge. In standby mode, SO pin of the device is High-Z.

3. When correct command is inputted to this device, it enters active mode and remains in active mode until next

CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as "Figure 1. Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDCR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ,

QREAD, RDSFDP, RES, REMS, the shifted-in instruction sequence is followed by a data-out sequence. After

any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE,

BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, SUSPEND, RESUME, NOP, RSTEN, RST, the CS#

must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. While a Write Status Register, Program or Erase operation is in progress, access to the memory array is

neglected and will not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

SCLK

MSB

CPHA

shift in

shift out

CPOL

(Serial mode 0)

(Serial mode 3) 1

SCLK

MSB

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