MX25R8035F datasheet(29/89 Pages) MCNIX

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ADVANCED INFORMATION

REV. 0.01, JAN. 06, 2015

MX25R8035F

P/N: PM2164

Configuration Register

The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured

after the CR bit is set.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”,

which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bit requires the Write Status Register (WRSR) instruction to be executed.

L/H switch bit

The Low Power / High Performance bit is a volatile bit. User can change the value of L/H switch bit to keep Low

Power mode or High Performance mode. The default value of the L/H switch bit is "0" after power on or reset,

which means that the device is at low power mode.

Configuration Register - 1

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Reserved

(top/bottom

selected)

Reserved

0=Top area

protect

1=Bottom

area protect

(Default=0)

OTP

Configuration Register - 2

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Reserved

L/H Switch

Reserved

0 = Low

power mode

(default)

1 = High

performance

mode

Volatile bit

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