MX25R8035F datasheet(31/89 Pages) MCNIX

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ADVANCED INFORMATION

REV. 0.01, JAN. 06, 2015

MX25R8035F

P/N: PM2164

9-9. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2,

BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR

also can set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in

accordance with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwise, the instruction will be

rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select

(CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in

progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the

Write Enable Latch (WEL) bit is reset. Please note that there is another parameter, "Write Status Register cycle time

for Mode Changing Switching (tWMS)", which is only for the self-timed of Mode Switching. For more detail please

check "Table 19. AC Characteristics".

Figure 13. Write Status Register (WRSR) Sequence

345678 9 10 11 12 13 14 15

Status

Configuration

MSB

SCLK

CS#

01h

High-Z

command

Mode 3

Mode 0

16 17 18 19 20 21 22 23

7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8

24 25 26 27 28 29 30 31

Configuration

23 22 21 20 19 18 17 16

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