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MX66L1G45G Scheda tecnica(PDF) 33 Page - Macronix International

Il numero della parte MX66L1G45G
Spiegazioni elettronici  3V 1G-BIT [x 1/x 2/x 4] CMOS MXSMIO
PDF  124 Pages
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Produttore elettronici  MCNIX [Macronix International]
Homepage  http://www.macronix.com
Logo MCNIX - Macronix International

MX66L1G45G Scheda tecnica(HTML) 33 Page - Macronix International

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MX66L1G45G
REV. 1.0, OCT. 01, 2014
P/N: PM2018
9-8. Read Configuration Register (RDCR)
The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at
any time (even in program/erase/write configuration register condition). It is recommended to check the Write in
Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation
is in progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→
Configuration
Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 23. Read Configuration Register (RDCR) Sequence (SPI Mode)
2
1
345678 9 10 11 12 13 14 15
command
0
7 6543210
Configuration register Out
High-Z
MSB
7 6543210
Configuration register Out
MSB
7
SCLK
SI
CS#
SO
15h
Mode 3
Mode 0
Figure 24. Read Configuration Register (RDCR) Sequence (QPI Mode)
0
1
3
SCLK
SIO[3:0]
CS#
15h
2
H0 L0
MSB LSB
4 5
7
H0 L0
6
H0 L0
H0 L0
Mode 3
Mode 0
Config.Byte
Config.Byte
Config.Byte
Config.Byte
N



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