MX66L1G45G datasheet(52/124 Pages) MCNIX

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MX66L1G45G

REV. 1.0, OCT. 01, 2014

P/N: PM2018

9-19. 2 x I/O Double Transfer Rate Read Mode (2DTRD)

The 2DTRD instruction enables Double Transfer Rate throughput on dual I/O of Serial Flash in read mode. The

address (interleave on dual I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on

dual I/O pins) shift out on both rising and falling edge of SCLK. The 4-bit address can be latched-in at one clock,

and 4-bit data can be read out at one clock, which means two bits at rising edge of clock, the other two bits at falling

edge of clock. The first address byte can be at any location.

The address is automatically increased to the next higher address after each byte data is shifted out, so the whole

memory can be read out at a single 2DTRD instruction. The address counter rolls over to 0 when the highest

address has been reached. Once writing 2DTRD instruction, the following address/dummy/ data out will perform as

4-bit instead of previous 1-bit.

The sequence of issuing 2DTRD instruction is: CS# goes low → sending 2DTRD instruction (1-bit per clock) → 24-

bit address interleave on SIO1 & SIO0 (4-bit per clock) → 6-bit dummy clocks (Default) on SIO1 & SIO0 → data

out interleave on SIO1 & SIO0 (4-bit per clock) → to end 2DTRD operation can use CS# to high at any time during

data out.

While Program/Erase/Write Status Register cycle is in progress, 2DTRD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 39. Fast Dual I/O DT Read (2DTRD) Sequence (SPI Only)

BDh

SI/SIO0

SO/SIO1

CS#

A22 A20

A23 A21

A2 A0

A3 A1

SCLK

D6 D4 D2 D0 D6 D4 D2 D0 D6

D7 D5 D3 D1 D7 D5 D3 D1 D7

Data Out

…

Command

6 ADD Cycles

Configurable

Dummy Cycle

Mode 3

Mode 0

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

configuration register.

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