MX66L1G45G datasheet(45/124 Pages) MCNIX

45 / 124 page

MX66L1G45G

REV. 1.0, OCT. 01, 2014

P/N: PM2018

9-13. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ

instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_

READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 32. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)

345678 9 10

28 29 30 31

22 21

3210

High-Z

32 33 34

36 37 38 39 40 41 42 43 44 45 46

76543 2

DATA OUT 1

Configurable

Dummy Cycle

MSB

7 6543210

DATA OUT 2

MSB

76543 2

SCLK

CS#

SCLK

CS#

0Bh

Command

Mode 3

Mode 0

24-Bit Address

(Note)

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

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