MX66L1G45G datasheet(6/124 Pages) MCNIX

6 / 124 page

MX66L1G45G

REV. 1.0, OCT. 01, 2014

P/N: PM2018

2. GENERAL DESCRIPTION

MX66L1G45G is 1Gb bits serial Flash memory, which is configured as 134,217,728 x 8 internally. When it is in

two or four I/O mode, the structure becomes 536,870,912 bits x 2 or 268,435,456 bits x 4. MX66L1G45G feature

a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O

mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial

access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX66L1G45G MXSMIO

 (Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX66L1G45G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read performance Comparison

Numbers of

Dummy Cycles

Fast Read

(MHz)

Dual Output

Fast Read

(MHz)

Quad Output

Fast Read

(MHz)

Dual IO

Fast Read

(MHz)

Quad IO

Fast Read

(MHz)

84*

133

104

84*

133*

133

104

166

133

Note: * mean default status

Numbers of

Dummy Cycles

Fast DTR Read

(MHz)

Dual I/O DT Read

(MHz)

Quad I/O DT Read

(MHz)

52*

66*

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