MX66L1G45G datasheet(46/124 Pages) MCNIX

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MX66L1G45G

REV. 1.0, OCT. 01, 2014

P/N: PM2018

9-14. Dual Output Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD

instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD

instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to define EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte or 4-byte

address on SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD

operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 33. Dual Read Mode Sequence

High Impedance

345678

SCLK

SI/SIO0

SO/SIO1

CS#

30 31 32

39 40 41

43 44 45

D6 D4

D7 D5

Command

24 ADD Cycle

Configurable

Dummy Cycle

A23 A22

A1 A0

…

Data Out

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit7 (DC0 & DC1) setting in

configuration register.

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