VPC3232D datasheet(33/78 Pages) MICRONAS

33 / 78 page

ADVANCE INFORMATION

VPC 323xD, VPC 324xD

Micronas

h’23

w/r

OUTPUT STRENGTH:

bit[3:0]

0..15

output pin strength

(0 = strong, 15 = weak)

bit[9:4]

address of output pin

FIFO control pins FFIE, FFOE, FFWR,

FFRE and FFRSTWR

SYNC pins AVO, HS, HC, INTERLACE, VS

bit[10]

0/1

read/write output strength

bit[15:11]

reserved (set to 0)

OUTSTR

PADSTR

PADADD

PADWR

h’30

w/r

V-SYNC DELAY CONTROL:

bit[7:0]

VS delay (8 LLC clock cycles per LSB)

VSDEL

656 Interface

h’24

w/r

656 OUTPUT INTERFACE

bit [0]

disable hor. & vert. blanking of invalid

data in 656 mode

bit [1]

use vertical window as VFLAG

use vsync as VFLAG

bit [2]

enable suppression of 656-headers

during invalid video lines

bit [3]

enable ITU-656 output format

bit [4]

0/1

LLC1/LLC2 used as reference clock

bit [5]

0/1

output mode: DIGIT 3000 / LLC

OUT656

DBLNK

VSMODE

HSUP

656enable

DBLCLK

OMODE

Sync Generator

h’21

w/r

LINE LENGTH:

bit[10:0]

LINE LENGTH register

In LLC mode, this register defines the

cycle of the sync counter which generates

the SYNC pulses.

In LLC mode, the synccounter counts from

0 to LINE LENGTH, so this register has to

be set to “number of pixels per line –1”.

In DIGIT3000 mode, LINE LENGTH has to

be set to 1295 for correct adjustment of

vertical signals.

bit[15:11]

reserved (set to 0)

1295

LINLEN

h’26

w/r

HC START:

bit[10:0]

HC START defines the beginning of the

HC signal in respect to the value of the

sync counter.

bit[15:11]

reserved (set to 0)

HCSTRT

h’27

w/r

bit[10:0]

HC STOP defines the end of the HC signal

in respect to the value of the sync counter.

bit[15:11]

reserved (set to 0)

800

HCSTOP

I2C Sub-

address

Number

of bits

Mode

Function

Default

Name

VPC3232D Scheda tecnica(PDF) 33 Page - Micronas

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