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VPC3232D Scheda tecnica(PDF) 7 Page - Micronas |
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VPC3232D Scheda tecnica(HTML) 7 Page - Micronas |
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7 / 78 page ![]() ADVANCE INFORMATION VPC 323xD, VPC 324xD Micronas 7 1.3. VPC Applications Fig. 1–2 depicts several VPC applications. Since the VPC functions as a video front-end, it must be comple- mented with additional functionality to form a complete TV set. The DDP 33x0 contains the video back-end with video postprocessing (contrast, peaking, DTI,...), H/V-deflec- tion, RGB insertion (SCART, Text, PIP,...) and tube control (cutoff, white drive, beam current limiter). It generates a beam scan velocity modulation output from the digital YCrCb and RGB signals. Note that this signal is not generated from the external analog RGB inputs. The component interface of the VPC 32xxD provides a high-quality analog RGB interface with character inser- tion capability. It also allows appropriate processing of external sources, such as MPEG2 set-top boxes in transparent (4:2:2) quality. Furthermore, it transforms RGB/Fast Blank signals to the common digital video bus and makes those signals available for 100-Hz up- conversion or double-scan processing. In some Euro- pean countries (Italy), this feature is mandatory. The IP indicates memory based image processing, such as scan rate conversion, vertical processing (Zoom), or PAL+ reconstruction. The VPC supports memory based applications through line-locked clocks, syncs and data. Additionally, the VPC323xD provides a 656-output interface and FIFO control signals. Examples: – Europe: 15 kHz/50 Hz → 32 kHz/100 Hz interlaced – US: 15 kHz/60 Hz → 32 kHz/60 Hz non-interlaced Fig. 1–2: VPC 32xxD applications a) 15 kHz application Europe b) double scan application (US, Japan) with YCrCb inputs c) 100 Hz application (Europe) with RGBFB inputs b) c) RGB H/V RGB RGB Defl. H/V H/V Defl. Defl. DDP 3310B DDP 3310B DDP 3300A IP IP VPC 32xxD VPC 32xxD RGB VPC 32xxD CVBS YCrCb/RGBFB CVBS YCrCb CVBS YCrCb/RGBFB a) VPC 32xxD FIFO YCrCb/RGBFB CVBS |
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