VPC3232D datasheet(45/78 Pages) MICRONAS

45 / 78 page

ADVANCE INFORMATION

VPC 323xD, VPC 324xD

Micronas

h’47 –

h’4b

scaler1 window controls, see table

5 12-bit registers for control of the nonlinear scaling

This register is updated when the scaler mode register is written.

SCW1_0 – 4

h’4c –

h’50

scaler2 window controls, see table

5 12-bit registers for control of the nonlinear scaling

This register is updated when the scaler mode register is written.

SCW2_0 – 4

h’52

brightness register

bit[7:0]

luma brightness

−128...127

ITU-R output format: 16

CVBS output format:

−4

bit[9:8]

horizontal lowpass filter for Y/C

0bypass

1filter 1

2filter 2

3filter 3

bit[10]

horizontal lowpass filter for highresolution chroma

0/1

bypass/filter enabled

this register is updated when the scaler mode register is written

SCBRI

LPF2

CBW2

h’53

contrast register

bit[5:0]

luma contrast 0..63

ITU-R output format: 48

bit[7:6]

horizontal peaking filter

0broad

1med

2narrow

bit[10:8] peaking gain

no peaking... 7 max. peaking

bit[10]

peaking filter coring enable

0/1

bypass/coring enabled

this register is updated when the scaler mode register is written

SCCT

PFS

PKCOR

LLC Control Register

h’65

vertical freeze start

freeze llc pll for llc_start < line number < llc_stop

bit[11:0]

allowed values from –156...+156

–10

LLC_START

h’66

vertical freeze stop

freeze llc pll for llc_start < line number < llc_stop

bit[11:0]

allowed values from –156...+156

4LLC_STOP

h’69

h’6a

20 bit llc clock center frequency

12.27 MHz

−79437 = h’FEC9B2

13.5 MHz

174763 = h’02AAAB

14.75 MHz

194181 = h’02F685

16 MHz

–135927 = h’FDED08

18 MHz

174763 = h’02AAAB

42 = h’02A

2731 = h’AA

LLC_CLOCKH

LLC_CLOCKL

FP Sub-

address

Function

Default

Name

VPC3232D Scheda tecnica(PDF) 45 Page - Micronas

VPC3232D Scheda tecnica(HTML) 45 Page - Micronas

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