VPC3232D datasheet(34/78 Pages) MICRONAS

34 / 78 page

VPC 323xD, VPC 324xD

ADVANCE INFORMATION

Micronas

h’28

w/r

AVO START:

bit[10:0]

AVO START defines the beginning of the

AVO signal in respect to the value of the

sync counter.

bit[11]

reserved (set to 0)

bit[12]

0/1

dis/enable suppression of AVO during VBI

and invalid video lines

bit[13]

0/1

vertical standard for flywheel

(312/262 lines) used if FLW is set

bit[14]

0/1

disable interlace for flywheel

bit[15]

0/1

enable vertical free run mode (flywheel)

AVSTRT

AVOGATE

FLWSTD

DIS_INTL

FLW

h’29

w/r

AVO STOP:

bit[10:0]

AVO STOP defines the end of the AVO

signal in respect to the value of the

sync counter.

bit[15:11]

reserved for test picture generation

(set to 0 in normal operation)

bit[11]

0/1

disable/enable test pattern generator

bit[13:12]

luma output mode:

Y = ramp (240 ... 17)

Y = 16

Y = 90

Y = 240

bit[14]

0/1

chroma output: 422/411 mode

bit[15]

0/1

chroma output: pseudo color bar/zero

if LMODE = 0

AVSTOP

COLBAREN

LMODE

M411

CMODE

h’22

w/r

NEWLINE:

bit[10:0]

NEWLINE defines the readout start of the

next line in respect to the value of the sync

counter. The value of this register must be

greater than 31 for correct operation and

should be identical to AVOSTART (recom-

mended). In case of 1H-bypass mode for

scaler block, NEWLINE has no function.

bit[15:11]

reserved (set to 0)

NEWLIN

I2C Sub-

address

Number

of bits

Mode

Function

Default

Name

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