UCS1003-3 datasheet(38/138 Pages) MICROCHIP

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UCS1003-1/2/3

DS20005346B-page 38

 2014-2015 Microchip Technology Inc.

5.3

Discrete Input Pins

5.3.1

COMM_SEL/ILIM INPUT

The COMM_SEL/ILIM input determines the initial ILIM

settings and the Communications mode, as shown in

Table 11-1.

5.3.2

SEL INPUT

The SEL pin selects the polarity of the PWR_EN

control. If the SEL pin is high, the PWR_EN control is

active-high enable. If the SEL pin is low, the PWR_EN

control is active-low enable. In addition, if the

UCS1003-1 is not configured to operate in Stand-Alone

mode, the SEL pin determines the SMBus address.

See Table 11-2. The SEL pin state is latched upon

device power-up and further changes will have no

effect.

5.3.3

M1, M2 AND EM_EN INPUTS

The M1, M2 and EM_EN input controls determine the

Active mode and affect the power state (see Table 5-2

and Table 9-1). When these controls are all set to ‘0’

and PWR_EN is enabled, the UCS1003-1/2/3 Attach

and Removal Detection feature is disabled. In case of

the UCS1003-1 configured in SMBus mode, the M1,

M2 and EM_EN pin states will be ignored by the

UCS1003-1 if the PIN_IGN Configuration bit is set (see

Section 10.4.3 “Switch Configuration Register”

);

otherwise, the M1_SET, M2_SET and EM_EN_SET

Configuration bits (see Section 10.4.3 “Switch

Configuration Register”

) are checked along with the

pins.

5.3.4

PWR_EN INPUT

The PWR_EN control enables the port power switch to

be turned on if conditions are met and affects the power

state (see Table 5-2). The port power switch cannot be

closed if PWR_EN is disabled. However, if PWR_EN is

enabled, the port power switch is not necessarily

closed (see Section 5.1.4 “Active State Operation”).

Polarity is controlled by the SEL pin. In the case of the

UCS1003-1 configured in SMBus mode, the PWR_EN

pin state will be ignored by the UCS1003-1 if the

PIN_IGN Configuration bit is set (see Section 10.4.3

“Switch Configuration Register”

); otherwise, the

PWR_ENS Configuration bit (see Section 10.4.3

“Switch Configuration Register”

) is checked along

with the pin.

5.3.5

LATCH INPUT

The latch input control determines the behavior of the

Fault handling mechanism (see Section 7.5 “Fault

Handling Mechanism”

When the UCS1003-1 is configured to operate in

Stand-Alone mode (see Section 11.3 “Stand-Alone

Operating Mode”

), the latch control is available

exclusively via the LATCH pin (see Table 11-10). When

the UCS1003-1 is configured to operate in SMBus

mode, the latch control is available exclusively via the

LATCHS

Configuration

bit

(see

Section 10.4.3

“Switch Configuration Register”

5.3.6

S0 INPUT

The S0 control enables the Attach and Removal

Detection feature, and affects the power state (see

Table 5-2). When S0 is set to ‘1’, an Attach Detection

event must occur before the port power switch can be

turned on. When S0 is set to ‘0’, the Attach and

Removal Detection feature is not enabled.

When the UCS1003-1 is configured to operate in

SMBus mode (see Section 11.3 “Stand-Alone Oper-

ating Mode”

), the S0 control is available exclusively

via the S0_SET Configuration bit (see Section 10.4.3

“Switch Configuration Register”

). Otherwise, the S0

control is available exclusively via the S0 pin since the

SMBus protocol will be disabled.

Note:

If it is necessary to connect any of the

control pins, except the COMM_SEL/ILIM

or SEL pins, via a resistor to VDD or GND,

the resistor value should not exceed

100 k

 in order to meet the VIH and VIL

specifications.

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