UCS1003-3 datasheet(77/138 Pages) MICROCHIP

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DS20005346B-page 77

UCS1003-1/2/3

10.4.3

SWITCH CONFIGURATION

The contents of this register are retained in Sleep.

R/W-0

U-0

R/W-0

R/W-1

R/W-0

PIN_IGN

—

EM_EN_SET

M2_SET

M1_SET

S0_SET

PWR_ENS

LATCHS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PIN_IGN:

Pin Ignore Selection Mode Determination bit

Ignores the M1, M2, PWR_EN and EM_EN pin states when determining the Active mode selection and

power state.

= The Active mode selection and power state will be set by the individual control bits and not by the

M1, M2, PWR_EN and EM_EN pin states; these pin states are ignored.

= The Active mode selection and power state will be set by the OR’d combination of the M1, M2,

PWR_EN and EM_EN pin states and the corresponding bit states.

bit 6

Unimplemented:

Read as ‘0’

bit 5

EM_EN_SET:

EM_EN Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”

) and power state (see Table 5-2). This bit is OR’d with the EM_EN pin.

bit 4

M2_SET:

M2 Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”

) and power state (see Table 5-2). This bit is OR’d with the M2 pin.

bit 3

M1_SET:

M1 Pin Selection Mode Determination bit

In conjunction with other controls, determines the Active mode that is selected (see Section 9.2 “Active

Mode Selection”

) and power state (see Table 5-2). This bit is OR’d with the M1 pin.

bit 2

S0_SET:

SMBus Mode Attach/Removal Detection bit

In SMBus mode, enables the Attach and Removal Detection feature and affects the power state (see

Section 9.2 “Active Mode Selection”

= Detection is enabled; also see Table 5-2

= Detection is not enabled; also see Table 5-2

bit 1

PWR_ENS:

Port Power Switch State bit

Controls whether the port power switch may be turned on or not and affects the power state (see

Section 5.3.4 “PWR_EN Input”

). This bit is OR’d with the PWR_EN pin and the polarity of both are

controlled by SEL pin decode. Thus, if the polarity is set to active-high, either the PWR_EN pin or this

bit must be ‘1’ to enable the port power switch.

bit 0

LATCHS:

SMBus Mode Fault Handling Routine Control bit

In SMBus mode, controls the Fault handling routine that is used in the case that an error is detected (see

Section 5.3.5 “Latch Input”

= The UCS1003-1 will latch its error conditions; in order for the device to return to normal Active state,

the ERR bit must be cleared by the user

= The UCS1003-1 will automatically retry when an error condition is detected

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