UCS1003-3 datasheet(66/138 Pages) MICROCHIP

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UCS1003-1/2/3

DS20005346B-page 66

 2014-2015 Microchip Technology Inc.

INTERRUPT STATUS REGISTER (ADDRESS 10h)

R/W-0

R-0

ERR(1,2)

DISCH_ERR

RESET

KEEP_OUT

TSD

OV_VOLT

BACK_V

OV_LIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ERR:

Error Detection Status bit(1,2)

Indicates that an error was detected and the device has entered the Error state. Writing this bit to a ‘0’

will clear the Error state and allows the device to be returned to the Active state. When written to ‘0’, all

error conditions are checked. If all error conditions have been removed, the UCS1003-1 returns to the

Active state. This bit is set automatically by the UCS1003-1 when the Error state is entered. Regardless

of the Fault handling mechanism used, if any other bit is set in the Interrupt Status register (10h), the

device will not leave the Error state.

This bit is cleared automatically by the UCS1003-1 if the auto-recovery Fault handling functionality is

active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is

disabled.

= One or more errors have been detected and the UCS1003-1 has entered the Error state

= There are no errors detected.

bit 6

DISCH_ERR:

Discharge VBUS Error Status bit

Indicates that the UCS1003-1 was unable to discharge the VBUS node. This bit will be cleared when read

if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT# pin

to be asserted and the device to enter the Error state.

= UCS1003-1 was unable to discharge the VBUS node

= No VBUS discharge error.

bit 5

RESET:

Reset Status bit

Indicates that UCS1003-1 has just been reset and should be reprogrammed. This bit will be set at

power-up. This bit is cleared when read or when the PWR_EN control is toggled. The ALERT# pin is not

asserted when this bit is set. This data is retained in the Sleep state.

= UCS1003-1 has just been reset

= Reset did not occur.

bit 4

KEEP_OUT:

V-I Output on VBUS Pins Status bit

Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN. This bit will be cleared when

read if the error condition has been removed or if the ERR bit is cleared. This bit will cause the ALERT#

pin to be asserted and the device to enter the Error state.

= VBUS < VBUS_MIN

= VBUS > VBUS_MIN

bit 3

TSD:

TTSD Threshold Internal Temperature Status bit

Indicates that the internal temperature has exceeded the TTSD threshold and the device has entered the

Error state. This bit will be cleared when read if the error condition has been removed or if the ERR bit

is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

= Internal temperature > TTSD

= Internal temperature < TTSD

Note 1:

If the auto-recovery Fault handling is not used, the ERR bit must be written to a logic ‘0’ to be cleared. It

will also be cleared when the PWR_EN control is disabled.

Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin may be

cleared or asserted without the ERR bit changing states.

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