SST25WF010 datasheet(12/36 Pages) MICROCHIP

12 / 36 page

DS20005016C

11/14

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash

SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040

EOL Data Sheet

1. One bus cycle is eight clock periods.

2. Address bits above the most significant bit of each density can be VIL or VIH.

3. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.

4. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.

5. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of

data to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be

programmed into the

initial address [A23-A1] with A0 =1.

6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

7. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides back-

ward compatibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.

8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufac-

turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.

Table 10: Device Operation Instructions for SST25WF020 AND SST25WF040

Instruction

Description

Op Code Cycle1

Address

Cycle(s)2

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Read

Read Memory

0000 0011b (03H)

1 to



20 MHz

High-Speed Read Read Memory at Higher

Speed

0000 1011b (0BH)

1 to



40 MHz

4 KByte Sector-

Erase3

Erase 4 KByte of memory

array

0010 0000b (20H)

32 KByte Block-

Erase4

Erase 32 KByte block

of memory array

0101 0010b (52H)

64 KByte Block-

Erase5

Erase 64 KByte block

of memory array

1101 1000b (D8H)

Chip-Erase

Erase Full Memory Array

0110 0000b (60H)

1100 0111b (C7H)

Byte-Program

To Program One Data Byte

0000 0010b (02H)

AAI-Word-Pro-

gram6

Auto Address Increment

Programming

1010 1101b (ADH)

2 to



RDSR7

Read-Status-Register

0000 0101b (05H)

1 to



EWSR8

Enable-Write-Status-Regis-

ter

0110 0000b (50H)

WRSR

Write-Status-Register

0000 0001b (01H)

WREN8

Write-Enable

0000 0110b (06H)

WRDI

Write-Disable

0000 0100b (04H)

RDID9

Read-ID

1001 0000b (90H)

1010 1011b (ABH)

1 to



EBSY

Enable SO to output RY/

BY# status during AAI pro-

gramming

0111 0000b (70H)

DBSY

Disable SO to output RY/

BY# status during AAI pro-

gramming

1000 0000b (80H)

JEDEC-ID

JEDEC ID read

1001 1111b (9FH)

3 to



EHLD

Enable HOLD# pin function-

ality of the RST#/HOLD# pin

1010 1010b (AAH)

T10.0

20005016

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