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DS20005016C

11/14

19

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash

SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040

EOL Data Sheet

64-KByte Block-Erase for SST25WF020 and SST25WF040

The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase

instruction applied to a protected memory area is ignored. Prior to any Write operation, the Write-Enable

(WREN) instruction must be executed. CE# must remain active low for the duration of any command

sequence. The Block-Erase instruction is initiated by executing an 8-bit command, D8H, followed by

nal self-timed Block-Erase. See Figure 15 for the Block-Erase sequences.

Figure 15:64-KByte Block-Erase Sequence

Chip-Erase

The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction is ignored if

any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must

be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The

Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE# must be driven high

for the completion of the internal self-timed Chip-Erase cycle. See Figure 16 for the Chip-Erase

sequence.

Figure 16:Chip-Erase Sequence

CE#

SO

SI

SCK

ADDR

01 2 3 4 5 6 7 8

ADDR

ADDR

D8

HIGH IMPEDANCE

15 16

23 24

31

MODE 0

MODE 3

1328 F15.0

MSB

MSB

CE#

SO

SI

SCK

01 2 3 4 5 6 7

60 or C7

HIGH IMPEDANCE

MODE 0

MODE 3

1328 F16.0

MSB