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SST25WF010 Scheda tecnica(PDF) 14 Page - Microchip Technology |
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SST25WF010 Scheda tecnica(HTML) 14 Page - Microchip Technology |
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14 / 36 page ![]() ©2014 Silicon Storage Technology, Inc. DS20005016C 11/14 14 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 EOL Data Sheet High-Speed-Read (40 MHz) The High-Speed-Read instruction supporting up to 40 MHz Read is initiated by executing an 8-bit com- mand, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 7 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci- fied address location. The data output stream is continuous through all addresses until terminated by a low-to-high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. For example, for 2 Mbit density, once the data from address location 3FFFFH is read, the next output will be from address location 000000H. Figure 7: High-Speed-Read Sequence 1328 F07.0 CE# SO SI SCK ADD. 012 34 5 6 7 8 ADD. ADD. 0B HIGH IMPEDANCE 15 16 23 24 31 32 39 40 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 X MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT 80 71 72 DOUT MSB |
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