CS53L30 datasheet(1/67 Pages) CIRRUS

Il numero della parte	CS53L30

Spiegazioni elettronici	Low-Power Quad-Channel Microphone ADC with TDM Output

PDF	67 Pages

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Produttore elettronici	CIRRUS [Cirrus Logic]

Homepage	http://www.cirrus.com

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Copyright

 Cirrus Logic, Inc. 2013–2015

http://www.cirrus.com

Low-Power Quad-Channel Microphone ADC with TDM Output

Analog Input and ADC Features



91-dB dynamic range (A-weighted) @ 0-dB gain



–84-dB THD+N @ 0-dB gain



Four fully differential inputs: Four analog mic/line inputs



Four analog programmable gain amplifiers



–6 to +12 dB, in 0.5-dB steps



+10 or +20 dB boost for mic input



Four mic bias generators



MUTE pin for quick mic mute and programmable quick

power down

Digital Processing Features



Volume control, mute, programmable high-pass filter,

noise gate



Two digital mic (DMIC) interfaces

Digital Output Features



Two DMIC SCLK generators



Four-channel I2S output or TDM output. Four CS53L30s

can be used to output 16 channels of 24-bit 16-kHz

sample rate data on a single TDM line.

System Features



Native (no PLL required) support for 6-/12-MHz, 6.144-/

12.288-MHz, 5.6448-/11.2896-MHz, or 19.2-MHz master

clock rates and 8- to 48-kHz audio sample rates



Master or Slave Mode. Clock dividers can be used to

generate common audio clocks from single-master clock

input.



Low power consumption



Less than 4.5-mW stereo (16 kHz) analog mic record



Less than 2.5-mW mono (8 kHz) analog mic record



Selectable mic bias and digital interface logic voltages



High-speed (400-kHz) I²C control port



Available in 30-ball WLCSP and 32-pin QFN

Applications



Voice-recognition systems



Advanced headsets and telephony systems



Voice recorders



Digital cameras and video cameras

CS53L30

Digital Processing

Control

Port

Level Shifters

MIC 1_BIAS

Serial Port

MIC 2_BIAS

VP

MCLK

DMIC1_SCLK

MIC3_BIAS

MIC4_BIAS

–6 to +12 dB,

0.5 dB steps

+10 or +20 dB

ADC1B

–

+

–

+

MIC1 Bias

MIC2 Bias

MIC3 Bias

MIC4 Bias

HPF, Noise

Gate, Volume,

Mute

Audio

Serial Port

Control Port

RESET

MCLK_INT

Clock Divider

Synchronizer

DMIC

ADC1A

–

+

LDO

VA

VD

2

4

MCLK_INT

HPF, Noise

Gate, Volume,

Mute

SYNC

MUTE

Synchronous

SRC

IN1+/DMIC1_SD

IN2–

IN1–

IN2+

DMIC2_SCLK

–

+

–6 to +12 dB,

0.5 dB steps

+10 or +20 dB

ADC2B

–

+

–

+

ADC2A

–

+

MCLK_INT

IN3+/DMIC2_SD

IN4–

IN3–

IN4+

–

+

CS53L30

DS992F2

MAR '15

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