CS53L30 datasheet(14/67 Pages) CIRRUS

14 / 67 page

DS992F2

CS53L30

3 Characteristics and Specifications

Table 3-10. Switching Specifications—Digital Mic Interface

Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L30 connections; GNDA = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VA, typical performance data taken with VA = 1.8 V, VP = 3.6 V, min/max performance data taken with VA = 1.8 V, VP = 3.6 V;

TA = +25°C; logic 0 = ground, logic 1 = VA; DMIC_DRIVE = 0 (normal); input timings are measured at VIL and VIH thresholds, and output timings are

measured at VOL and VOH thresholds (see Table 3-14).

Parameters 1,2

1.Digital mic interface timing

2.Oversampling rate of the digital mic must match the oversampling rate of the CS53L30 internal decimators.

Symbol

Min

Max

Units

Output clock (DMICx_SCLK) frequency

1/tP

—3.2[3]

3.The output clock frequency follows the internal MCLK rate divided by 2 or 4, as set in the ADCx/DMICx control registers (see DMIC1_SCLK_DIV on

p. 53 and DMIC2_SCLK_DIV on p. 55). DMICx_SCLK is further divided by up to a factor of 4 when MCLK_INT_SCALE is set (see p. 48). MCLK

source deviation from nominal supported rates is applied directly to the output clock rate by the same factor (e.g., a +100-ppm offset in the frequency

of MCLK becomes a +100-ppm offset of DMICx_SCLK.

MHz

DMICx_SCLK duty cycle4

—45

DMICx_SCLK rise time (10% to 90% of VA) 4

4.Timing guaranteed with pull-up or pull-down resistor, with a minimum value 10 k

tied to DMIC2_SCLK/AD1 for I2C address determination.

—21

DMICx_SCLK fall time (90% to 10% of VA) 4

—13

DMICx_SD setup time before DMICx_SCLK rising edge

ts(SD-CLKR)

—

DMICx_SD hold time after DMICx_SCLK rising edge

th(CLKR-SD)

4—

DMICx_SD setup time before DMICx_SCLK falling edge

ts(SD-CLKF)

—

DMICx_SD hold time after DMICx_SCLK falling edge

th(CLKF-SD)

4—

Table 3-11. Specifications—I2S

Test conditions (unless specified otherwise): Fig. 2-1 shows CS53L30 connections; GNDA = GNDD = 0 V; all voltages are with respect to ground;

parameters can vary with VA; typical performance data taken with VA = 1.8 V, VP = 3.6 V; min/max performance data taken with VA = 1.8 V, VP = 3.6 V;

TA = +25°C; Test load for ASP_LRCK/FSYNC, ASP_SCLK, and ASP_SDOUTx CL = 60 pF; logic 0 = ground, logic 1 = VA; ASPx_DRIVE = 0; input

timings are measured at VIL and VIH thresholds, and output timings are measured at VOL and VOH thresholds (see Table 3-14).

Parameters 1,2

1.Serial port

interface timing

2.MCLK must be stable before powering up the device. In Slave Mode, ASP_LRCK/FSYNC and ASP_SCLK must be stable before powering up the

device. Before making changes to any clock setting, the device must be powered down by setting either the PDN_ULP or PDN_LP bit.

Symbol

Min

Max

Units

MCLK frequency

—

1.024

19.2

MHz

MCLK duty cycle

—

Slave mode

Input sample rate (LRCK)

(See Table 4-2)kHz

LRCK duty cycle

—

SCLK frequency

1/tPs

—

64•Fsext

SCLK duty cycle

—

SCLK rising edge to LRCK edge

ths(LK-SK)

—

LRCK setup time before SCLK rising edge

tss(LK-SK)

—

SDOUT setup time before SCLK rising edge

tss(SDO-SK)

—

SDOUT hold time after SCLK rising edge

ths(SK-SDO)

—

Master mode Output sample rate (LRCK) All speed modes

Fsext

(See Table 4-2)kHz

LRCK duty cycle

—

SCLK frequency

1/tPm

—

64•Fsext

SCLK duty cycle

—

LRCK time before SCLK falling edge

tsm(LK-SK)

–2

SDOUT setup time before SCLK rising edge

tsm(SDO-SK)

—

SDOUT hold time after SCLK rising edge

thm(SK-SDO)

—

DMIC_CLK

DMIC_SD

Left

(A, DATA1 )

Channel Data

Right

(B , DATA2)

Channel Data

Left

(A, DATA1)

Channel Data

thm(SK-SDO)

MSB

LRCK

SCLK

SDOUT

tPm

tsm(SDO-SK)

tsm(LK-SK)

ths(SK-SDO)

MSB

LRCK

SCLK

SDOUT

tss(LK-SK)

tss(SDO-SK)

ths(LK-SK)

Serial Port Timing—Master Mode

Serial Port Timing—Slave Mode

CS53L30 Scheda tecnica(PDF) 14 Page - Cirrus Logic

CS53L30 Scheda tecnica(HTML) 14 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Scheda tecnica Scarica

Link URL