CS53L30 datasheet(44/67 Pages) CIRRUS

44 / 67 page

DS992F2

CS53L30

5.5 MCLK Jitter

The following analog and digital specifications listed in Section 3 are affected by MCLK jitter:

• INx-to-x_SDOUT THD+N

The effect of MCLK jitter on THD+N is due to sampling at an unintended time, resulting in sample error. The resulting

sample error is a function of the time error as a result of MCLK jitter and of the slope of the signal being sampled or

reconstructed. To achieve the specified THD+N characteristics listed in Section 3, the MCLK jitter should not exceed 1 ns

peak-to-peak. The absolute jitter of a standard crystal oscillator is typically below 100-ps peak-to-peak and should meet

the previously stated requirements.

5.6 Frequency Response Considerations

The ADC and SRC combined response referred to in Table 3-3 shows the response from the capture-path inputs to the

serial port outputs. This path includes two contributions to the frequency response of the CS53L30:

• ADC data path

• Synchronous SRC data path

The internal sample rate (Fsint) of the CS53L30 is determined by MCLK, INTERNAL_FS_RATIO, MCLK_19MHZ_EN, and

MCLK_INT_SCALE (see Table 4-2). The external sample rate (Fsext) is set by ASP_RATE. When the Fsint and the Fsext

are equal, the combined response of the ADC and the SRC has a lower –3-dB corner frequency than either would have

alone. When Fsext is lower than Fsint, the frequency response of the SRC dominates; as a result, the combined frequency

response has a higher –3 dB corner frequency than if Fsint and Fsext were equal.

5.7 Connecting Unused Pins

Unused pins may be terminated or left unconnected, according to the recommendations in the following sections.

5.7.1

Analog Inputs

Unused differential analog input pin pairs (INx+ and INx-) may be left unconnected or tied directly to ground. If the pins are

left unconnected, the input bias should be configured as weak pull-down (INxy_BIAS = 01). If the pins are tied directly to

ground, the input bias should be configured as open (INxy_BIAS = 00) or weak pull-down (INxy_BIAS = 01). To minimize

power consumption, the ADC associated with an unused differential input pin pair may be powered down.

When using single-ended inputs, the INx- pin must be tied to ground through a DC-blocking capacitor as shown in Fig. 4-7.

The same capacitor value should be used on both pins of the input pair (INx+ and INx-). Tying the INx- pin directly to

ground may cause unexpected frequency response or distortion performance.

5.7.2

DMIC inputs

When the input channel type is set to digital, the input bias should be configured as weak pull-down (INxy_BIAS = 01) for

all used and unused channels. Unused input pins may be left unconnected or tied directly to ground. The FILT+ pin may

be left unconnected.

5.7.3

Mic Bias

Unused mic bias output pins (MICx_BIAS) may be left unconnected. If unconnected, the mic bias should be powered down

(MICx_BIAS_PDN = 1). If none of the mic bias outputs are used, the mic bias filter pin (MIC_BIAS_FILT) may also be left

unconnected.

CS53L30 Scheda tecnica(PDF) 44 Page - Cirrus Logic