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Motore di ricerca datesheet componenti elettronici |
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R5F572TFGDFP Scheda tecnica(PDF) 145 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 145 Page - Renesas Technology Corp |
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145 / 176 page  R01DS0331EJ0100 Rev.1.00 Page 145 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics Note 1. tPBcyc: PCLKB cycle; tPAcyc: PCLKA cycle Note 2. When the SEMR.ABCS and SEMR.BGDM bits are set to 1 Table 5.33 SCIj, SCIh, and SCIi Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Max. Unit*1 Test Conditions SCIj, SCIh Input clock cycle Asynchronous tScyc 4 — tPBcyc Figure 5.45 Clock synchronous 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 8— tPBcyc Clock synchronous 4 — Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Clock synchronous tTXD — 28 ns VCC ≥ 4.5 V Figure 5.46 — 33 VCC < 4.5 V Receive data setup time Clock synchronous tRXS 15 — ns VCC ≥ 4.5 V Figure 5.46 20 — VCC < 4.5 V Receive data hold time Clock synchronous tRXH 5 — ns Figure 5.46 SCIi Input clock cycle Asynchronous tScyc 4— tPAcyc Figure 5.45 Clock synchronous 6 — Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr —5 ns Input clock fall time tSCKf —5 ns Output clock cycle Asynchronous*2 tScyc 6— tPAcyc Clock synchronous 4 — Output clock pulse width tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr —5 ns Output clock fall time tSCKf —5 ns Transmit data delay time Master tTXD — 15 ns VCC ≥ 4.5 V Figure 5.46 Slave — 28 Master — 20 VCC < 4.5 V Slave — 33 Receive data setup time Clock synchronous tRXS 15 — ns VCC ≥ 4.5 V Figure 5.46 20 — VCC < 4.5 V Receive data hold time Clock synchronous tRXH 5 — ns Figure 5.46 |
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