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R5F572TFGDFP Scheda tecnica(PDF) 149 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 149 Page - Renesas Technology Corp |
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149 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 149 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics Figure 5.47 RSPI Clock Timing and Simple SPI Clock Timing Figure 5.48 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKA Division Ratio Set to a Value Other Than 1/2) and Simple SPI Timing (Master, CKPH = 1) RSPCKA master select output RSPCKA slave select input tSPCKWH VOH VOH VOL VOL VOH VOH tSPCKWL tSPCKr tSPCKf VOL tSPcyc tSPCKWH VIH VIH VIL VIL VIH VIH tSPCKWL tSPCKr tSPCKf VIL tSPcyc VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC RSPI Simple SPI (n = 1, 5, 6, 8, 9, 11, 12) SCKn master select output SCKn slave select input tDr, tDf tSU tH tLEAD tTD tLAG tSSLr, tSSLf tOH tOD MSB IN DATA LSB IN MSB IN MSB OUT DATA LSB OUT IDLE MSB OUT SSLA0 to SSLA3 output RSPCKA CPOL = 0 output RSPCKA CPOL = 1 output MISOA input MOSIA output RSPI SCKn CKPOL = 0 output SCKn CKPOL = 1 output SMISOn input SMOSIn output Simple SPI (n = 1, 5, 6, 8, 9, 11, 12) |
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