R5F572TFGDFP datasheet(147/176 Pages) RENESAS

147 / 176 page

R01DS0331EJ0100 Rev.1.00

Page 147 of 176

Feb 08, 2019

RX72T Group

5. Electrical Characteristics

Note 1. tPAcyc: PCLKA cycle

Table 5.34

RSPI Timing

Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,

VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).

Item

Symbol

Min.*1

Max.*1

Unit*1

Test Conditions

RSPI

RSPCK clock

cycle

Master

tSPcyc

4096

tPAcyc Figure 5.47

Slave

—

RSPCK clock

high pulse width

Master

tSPCKWH (tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKr

– tSPCKf) / 2

—ns

RSPCK clock

low pulse width

Master

tSPCKWL (tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKr

– tSPCKf) / 2

—ns

RSPCK clock

rise/fall time

Output

tSPCKr,

tSPCKf

—5

Input

—

μs

Data input setup

time

Master

tSU

—

VCC ≥ 4.5 V Figure 5.48 to

Figure 5.53

—

VCC < 4.5 V

Slave

8.3

—

Figure 5.48 to Figure 5.53

Data input hold

time

PCLKA division

ratio set to 1/2

tHF

0—

PCLKA division

ratio set to a value

other than 1/2

tPAcyc

—

Slave

8.3

—

SSL setup time

Master

tLEAD

tSPcyc

Slave

—

tPAcyc

SSL hold time

Master

tLAG

tSPcyc

Slave

—

tPAcyc

Data output

delay time

Master

tOD

—

6.3

VCC ≥ 4.5 V Figure 5.48 to

Figure 5.53

Slave

—

Master

—

11.3

VCC < 4.5 V

Slave

—

Data output hold

time

Master

tOH

—

Figure 5.48 to Figure 5.53

Slave

—

Successive

transmission

delay time

Master

tTD

tSPcyc + 2 ×

tPAcyc

8 × tSPcyc

+ 2 × tPAcyc

Slave

6 × tPAcyc

—

MOSI and MISO

rise/fall time

Output

tDr, tDf

—5

Input

—

μs

SSL

rise/fall time

Output

tSSLr,

tSSLf

—5

Input

—

μs

Slave access time

tSA

—2 × tPAcyc + 28

VCC ≥ 4.5 V Figure 5.52,

Figure 5.53

—2 × tPAcyc + 33

VCC < 4.5 V

Slave output release time

tREL

—2 × tPAcyc + 28

VCC ≥ 4.5 V

—2 × tPAcyc + 33

VCC < 4.5 V

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