MCP47FXB2XT-EST datasheet(51/124 Pages) MICROCHIP

51 / 124 page

 2020 Microchip Technology Inc.

DS20006368A-page 51

MCP47FXBX4/8

3.1

Positive Power Supply Input (VDD)

VDD is the positive supply voltage input pin. The input

supply voltage is relative to VSS.

The power supply at the VDD pin should be as clean as

possible for a good DAC performance. It is

recommended to use an appropriate bypass capacitor

of about 0.1 µF (ceramic) to ground. An additional

10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate noise present in

application boards.

3.2

Ground (VSS)

The VSS pin is the device ground reference.

The user must connect the VSS pin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (Printed

Circuit Board), it is highly recommended that the VSS

pin be tied to the analog ground path or isolated within

an analog ground plane of the circuit board.

3.3

Voltage Reference Pins (VREF)

The VREF pin is either an input or an output. When the

DAC’s voltage reference is configured as the VREF pin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

When the DAC’s voltage reference is configured as the

VREF pin, there are two options for this voltage input:

•VREF pin voltage buffered

•VREF pin voltage unbuffered

The buffered option is offered in cases where the exter-

nal reference voltage does not have sufficient current

capability to not drop its voltage when connected to the

internal resistor ladder circuit.

When the DAC’s voltage reference is configured as the

device VDD, the VREF pin is disconnected from the

internal circuit.

When the DAC’s voltage reference is configured as the

internal band gap, the VREF pin’s drive capability is min-

imal, so the output signal should be buffered.

There are two VREF pins, each corresponding to a

group of output channels. VREF0 is connected to even

channels: 0-6, while VREF1 is connected to odd chan-

nels: 1-7. See Section 5.2 “Voltage Reference Selec-

tion” and Register 4-2 for more details on the

Configuration bits.

3.4

Analog Output Voltage Pins

(VOUTn)

VOUT is the DAC analog voltage output pin. The DAC

output has an output amplifier. The DAC output range

depends on the selection of the voltage reference

source (and potential output gain selection). These are:

• Device VDD – The full-scale range of the DAC out-

put is from VSS to approximately VDD.

•VREF pin – The full-scale range of the DAC output

is from VSS to G × VRL, where G is the gain selec-

tion option (1x or 2x).

• Internal Band Gap – The full-scale range of the

DAC output is from VSS to G × (2 × VBG), where G

is the gain selection option (1x or 2x).

In Normal mode, the DC impedance of the output pin is

about 1

. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

, 125 k, or open. The power-down selection bits

settings are shown in Register 4-3 and Table 5-4.

3.5

Latch Pin (LAT)/High-Voltage

Command (HVC)

The DAC output value update event can be controlled

and synchronized using the LAT pins, for one or both

channels, on a single or different devices.

The LAT pins control the effect of the Volatile Wiper

registers, VRnB:VRnA, PDnB:PDnA and Gx bits on the

DAC output.

If the LAT pins are held at VIH, the values sent to the

Volatile Wiper registers and Configuration bits have no

effect on the DAC outputs.

Once voltage on the pin transitions to VIL, the values in

the Volatile Wiper registers and Configuration bits are

transferred to the DAC outputs.

The pin is level-sensitive, so writing to the Volatile

Wiper registers and Configuration bits, while it is being

held at VIL, will trigger an immediate change in the

outputs.

The HVC pin allows the device’s nonvolatile user Con-

figuration bits to be programmed when the voltage on

the pin is greater than the VIHH entry voltage.

3.6

I2C - Serial Clock Pin (SCL)

The SCL pin is the serial clock pin of the I2C interface.

The MCP47FXBX4/8 I2C interface only acts as a slave

and the SCL pin accepts only external serial clocks.

The input data from the master device is shifted into the

SDA pin on the rising edges of the SCL clock and

output from the device occurs at the falling edges of the

SCL clock. The SCL pin is an open-drain, N-channel

driver. Therefore, it needs an external pull-up resistor

from the VDD line to the SCL pin. Refer to Section 6.0

“I2C Serial Interface Module” for more details on the

I2C serial interface communication.

MCP47FXB2XT-EST Scheda tecnica(PDF) 51 Page - Microchip Technology

MCP47FXB2XT-EST Scheda tecnica(HTML) 51 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL