MCP47FXB2XT-EST datasheet(93/124 Pages) MICROCHIP

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DS20006368A-page 93

MCP47FXBX4/8

8.0

APPLICATIONS INFORMATION

The MCP47FXBX4/8 devices are general purpose,

quad/octal-channel voltage output DACs for various

applications where a precision operation with low-power

and nonvolatile EEPROM memory is needed.

Since the devices include a nonvolatile EEPROM

memory, the user can utilize these devices for

applications that require the output to return to the

previous set-up value on subsequent power-ups.

8.1

I2C Bus Connection

Considerations

8.1.1

CONNECTING TO THE I2C BUS

USING PULL-UP RESISTORS

The SCL and SDA pins of the MCP47FXBX4/8 devices

are open-drain configurations. These pins require a

pull-up resistor, as shown in Figure 8-3.

The pull-up resistor values (R1 and R2) for SCL and

SDA pins depend on the operating speed (standard,

fast and high speed) and loading capacitance of the I2C

bus line. A higher value of the pull-up resistor consumes

less power, but increases the signal transition time

(higher RC time constant) on the bus line. Therefore, it

can limit the bus operating speed. The lower resistor

value, on the other hand, consumes higher power, but

allows higher operating speed. If the bus line has higher

capacitance due to long metal traces or multiple device

connections to the bus line, a smaller pull-up resistor is

needed to compensate the long RC time constant. The

pull-up resistor is typically chosen between 1 k

 and

10 k

ranges for Standard and Fast modes, and less

than 1 k

for High-Speed mode.

8.1.2

DEVICE CONNECTION TEST

The user can test the presence of the device on the I2C

bus line by using a simple I2C command. This test can

be achieved by checking an acknowledge response

from the device after sending a READ or WRITE

command. Figure 8-1 shows an example with a READ

command. The steps are:

Set the R/W bit “High” in the device’s address byte.

Check the ACK bit of the address byte.

If the device acknowledges (ACK = 0) the

command, then the device is connected.

Otherwise, it is not connected.

Send Stop bit.

FIGURE 8-1:

I2C Bus Connection Test.

8.1.3

SOFTWARE I2C INTERFACE RESET

SEQUENCE

At times, it may become necessary to perform a

Software

Reset

Sequence

ensure

the

MCP47FXBX4/8 devices are in a correct and known I2C

interface state. This technique only resets the I2C state

machine.

This is useful if the MCP47FXBX4/8 devices power-up

in an incorrect state (due to excessive bus noise, etc),

or if the master device is reset during communication.

Figure 8-2 shows the communication sequence to

software reset the device.

FIGURE 8-2:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which expects to receive data from the master

device. In this mode, the device monitors the data bus

in Receive mode and can detect if the Start bit forces

an internal reset.

The nine bits of ‘1’ are used to force a reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47FXBX4/8 devices drive

an A bit on the I2C bus, or are in Output mode (from a

READ command) and are driving a data bit of ‘0’ onto

the I2C bus. In both of these cases, the previous Start

bit could not be generated due to the MCP47FXBX4/8

holding the bus low. By sending out nine ‘1’ bits, it is

ensured that the device will see an A bit (the master

device does not drive the I2C bus low to acknowledge

the data sent by the MCP47FXBX4/8), which also

forces the MCP47FXBX4/8 to reset.

Note:

This technique is documented in AN1028.

12 3 4 5 6 7 8 9

SCL

SDA

A2 A1 A0 1

Start

Bit

Address byte

Address bits

R/W

Stop

Bit

Device

Response

S‘1’‘1’‘1’‘1’‘1’‘1’‘1’‘1’ S

Start bit

Nine bits of ‘1’

Start bit

Stop bit

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