MCP47FXB2XT-EST datasheet(55/124 Pages) MICROCHIP

55 / 124 page

 2020 Microchip Technology Inc.

DS20006368A-page 55

MCP47FXBX4/8

4.2

Device Memory

User memory includes the following types:

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory

• Device Configuration Memory

Each memory address is 16 bits wide. There are up to

17 nonvolatile user control bits that do not reside in

memory-mapped register space (see Section 4.2.3

“Device Configuration Memory”).

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

There are up to twelve volatile memory locations:

• DAC0 through DAC7 Output Value registers

•VREF Select register

• Power-Down Configuration register

• Gain and STATUS register

• WiperLock Technology STATUS register

The volatile memory starts functioning when the

device VDD is at (or above) the RAM retention voltage

(VRAM). The volatile memory will be loaded with the

default device values when the VDD rises across the

VPOR/VBOR voltage trip point.

4.2.2

NONVOLATILE REGISTER

MEMORY

This device family uses the nonvolatile memory for the

DAC output value and Configuration registers:

• Nonvolatile DAC0 through DAC7 Output Value

registers

• Nonvolatile VREF Select register

• Nonvolatile Power-Down Configuration register

• Nonvolatile Gain and I2C Address register

The nonvolatile memory starts functioning below the

device’s VPOR/VBOR trip point, and is loaded into the

corresponding volatile registers whenever the device

rises above the POR/BOR voltage trip point.

The device starts writing the nonvolatile (EEPROM)

memory location at the completion of the serial inter-

face command, after the Acknowledge pulse of the

WRITE Single command. Continuous write commands

addressing the nonvolatile memory are not permitted.

Nonvolatile DAC registers enable the stand-alone

operation of the device (without microcontroller control)

after being programmed to the desired value.

4.2.3

DEVICE CONFIGURATION

MEMORY

There are up to seventeen nonvolatile user bits that are

not directly mapped into the address space. These

nonvolatile device Configuration bits control the follow-

ing functions:

• WiperLock technology for DAC registers and Con-

figuration (2 bits per DAC)

•I2C Slave Address Write Protect (Lock)

The STATUS register shows the states of the device

WiperLock technology Configuration bits. The STA-

TUS register is described in Register 4-6.

The operation of WiperLock technology is discussed in

Section 4.2.6 “WiperLock Technology”, while I2C

Slave Address Write Protect is discussed in

Section 4.2.7 “I2C Slave Address Write Protect”.

4.2.4

UNIMPLEMENTED REGISTER BITS

READ commands of a valid location will read

unimplemented bits as ‘0’.

4.2.5

UNIMPLEMENTED (RESERVED)

LOCATIONS

Normal (voltage) commands (READ or WRITE) to any

unimplemented memory address (reserved) will result

in a command error condition (NACK). READ com-

mands of a reserved location will read bits as ‘1’.

High-Voltage commands (enable or disable) to any

unimplemented Configuration bits will result in a

command error condition (NACK).

4.2.5.1

Default Factory POR Memory State

of Nonvolatile Memory (EEPROM)

Table 4-2 shows the default factory POR initialization

of the device memory map for the 8, 10 and 12-bit

devices. In case of volatile memory devices

(MCP47FVBXX), the factory default values cannot be

modified.

Note:

When the nonvolatile memory is written,

the corresponding volatile memory is not

modified.

Note:

The volatile memory locations will be

determined by the nonvolatile memory

states (registers and device Configuration

bits).

MCP47FXB2XT-EST Scheda tecnica(PDF) 55 Page - Microchip Technology

MCP47FXB2XT-EST Scheda tecnica(HTML) 55 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL