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MCP47FXB2XT-EST Scheda tecnica(PDF) 85 Page - Microchip Technology |
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MCP47FXB2XT-EST Scheda tecnica(HTML) 85 Page - Microchip Technology |
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85 / 124 page ![]() 2020 Microchip Technology Inc. DS20006368A-page 85 MCP47FXBX4/8 FIGURE 7-5: READ Command – Last Memory Address Accessed. Note 1: The Acknowledge bit is generated by the MCP47FXBX4/8. 2: The master device is responsible for the A/A signal. If an A signal occurs, the MCP47FXBX4/8 will abort this transfer and release the bus. 3: The master device will Not Acknowledge, and the MCP47FXBX4/8 will release the bus so the master device can generate a Stop or repeated Start condition. 4: At the falling edge of the SCL pin for the READ command ACK bit, the MCP47FXBX4/8 device updates the value of the specified device register. 5: This command sequence does not need to terminate (using the Stop bit) and the READ command can be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”). I2C ACK bit (1) SA 6 S SA 5 SA 4 SA 3 SA 2 SA 1 SA 0 1 A A P S SA n I2C Start bit I2C Slave Address I2C Stop bit(5) D nn Data (read from memory) Control byte Legend: 0 0 0 0 D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 A P A Data Read MSB Data Read LSB A I2C ACK bit(2) I2C NACK bit(3, 4) A 1 I2C Read bit |
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