MB90F482 datasheet(61/113 Pages) FUJITSU

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MB90480/485 Series

14. Watchdog timer

The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as acount

clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated.

(1) Register List

(2) Block Diagram

Watchdog timer control register (WDTC)

0000A8H

Read/write

Initial value



PONR

WRST

ERST

SRST

WTE

WT1

WT0

Reserved

PONR

WRST ERST SRST WTE

WT1

WT0

× 21 × 22

× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

× 21

SCLK

CLR

× 22

× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

Watchdog timer control register (WDTC)

Watchdog timer

Watch mode start

Timebase timer

mode start

Sleep mode start

Hold status start

Counter

clear circuit

Count

clock

selector

2-bit

counter

Watchdog

reset

generator

circuit

Clear

Internal

reset

generator

circuit

CLR and

start

Time-base counter

HCLK

× 2

HCLK : Oscillator clock

SCLK : Sub clock

Watch timer control

WDCS bit

Clock select register

(CKSCR)

SCM bit

Stop mode

start

Re-

served

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