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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB90F482 Scheda tecnica(PDF) 90 Page - fujitsu semiconductor |
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MB90F482 Scheda tecnica(HTML) 90 Page - fujitsu semiconductor |
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90 / 113 page  MB90480/485 Series 90 (5) Bus Read Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) * : tCP : See “ (1) Clock Timing Standards”. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max ALE pulse width tLHLL ALE tCP* / 2 − 15 ns at fcp = 25 MHz tCP* / 2 − 20 ns at fcp = 16 MHz tCP* / 2 − 35 ns at fcp = 8 MHz Valid address → ALE ↓time tAVLL Address, ALE tCP* / 2 − 17 ns tCP* / 2 − 40 ns at fcp = 8 MHz ALE ↓→ address valid time tLLAX ALE, Address tCP* / 2 − 15 ns Valid address → RD ↓time tAVRL RD, address tCP* − 25 ns Valid address → valid data input tAVDV Address, Data 5 tCP* / 2 − 55 ns 5 tCP* / 2 − 80 ns at fcp = 8 MHz RD pulse width tRLRH RD 3 tCP* / 2 − 25 ns at fcp = 25 MHz 3 tCP* / 2 − 20 ns at fcp = 16 MHz RD ↓→ valid data input tRLDV RD, Data 3 tCP* / 2 − 55 ns 3 tCP* / 2 − 80 ns at fcp = 8 MHz RD ↑→data hold time tRHDX RD, Data 0 ns RD ↑→ALE↑rise time tRHLH RD, ALE tCP* / 2 − 15 ns RD ↑→ address valid time tRHAX Address, RD tCP* / 2 − 10 ns Valid address → CLK ↑time tAVCH Address, CLK tCP* / 2 − 17 ns RD ↓→CLK↑time tRLCH RD, CLK tCP* / 2 − 17 ns ALE ↓→RD↓time tLLRL RD, ALE tCP* / 2 − 15 ns |
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