MB90F482 datasheet(99/113 Pages) FUJITSU

99 / 113 page

MB90480/485 Series

(13) I2C Timing

(VCC

= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

*1 : fcp is internal operation clock frequency. Refer to “ (1) Clock Timing Standards”.

*2 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

Note : VCC

= VCC3 = VCC5

Parameter

Symbol

Condition

Standard-mode

Unit

Min

Max

SCL clock frequency

fSCL

When power supply voltage of

external pull-up resistance is 5.5 V

= 1.3 kΩ, C = 50 pF*2

When power supply voltage of

external pull-up resistance is 3.6 V

= 1.6 kΩ, C = 50 pF*2

100

kHz

Hold time (repeated) START condition

SDA

↓→SCL↓

tHDSTA

4.0

µs

“L” width of the SCL clock

tLOW

4.7

µs

“H” width of the SCL clock

tHIGH

4.0

µs

Set-up time (repeated) START

condition SCL

↑→SDA↓

tSUSTA

4.7

µs

Data hold time

SCL

↓→SDA↓↑

tHDDAT

3.45*3

µs

Data set-up time

SDA

↓↑→SCL↑

tSUDAT

When power supply voltage of

external pull-up resistance is 5.5 V

fcp*1

≤ 20 MHz, R = 1.3 kΩ, C = 50 pF*2

When power supply voltage of

external pull-up resistance is 3.6 V

fcp*1

≤ 20 MHz, R = 1.6 kΩ, C = 50 pF*2

250



When power supply voltage of

external pull-up resistance is 5.5 V

fcp*1

> 20 MHz, R = 1.3 kΩ, C = 50 pF*2

When power supply voltage of

external pull-up resistance is 3.6 V

fcp*1

> 20 MHz, R = 1.6 kΩ, C = 50 pF*2

200



Set-up time for STOP condition

SCL

↑→SDA↑

tSUSTO

When power supply voltage of

external pull-up resistance is 5.5 V

= 1.3 kΩ, C = 50 pF*2

When power supply voltage of

external pull-up resistance is 3.6 V

= 1.6 kΩ, C = 50 pF*2

4.0

µs

Bus free time between a STOP and

START condition

tBUS

4.7

µs

SDA

SCL

tLOW

tSUDAT

tHDSTA

tBUS

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

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