ADL5308ACCZ-R7 datasheet(13/22 Pages) AD

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Data Sheet

ADL5308

THEORY OF OPERATION

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Rev. 0 | 13 of 22

PHOTODIODE BIAS (PDB)

The PDB function maximizes the dynamic range of optical power

measurements by minimizing the impact of dark current and series

resistance on the measurement accuracy.

Dark current is a small leakage current through the diode that

does not change proportionally to the incident optical power, and

therefore limits the sensitivity of an optical power measurement.

Since it generally increases with the reverse bias voltage, a low

reverse bias voltage minimizes the dark current and maximizes the

sensitivity of the optical power measurement.

Series resistance introduces measurement errors at high current

levels through the PD. The voltage drop across this resistance

reduces the reverse bias voltage across the PD junction itself,

which may lead to saturation or even forward bias of the junction. A

sufficiently high reverse bias voltage, preferably proportional to the

diode current to maintain constant reverse bias across the junction,

is needed to minimize the impact of the PD series resistance.

The PDB function of the ADL5308 adjusts the reverse bias across

the PD as a function of the current through the PD, as shown

in Figure 30. At low PD currents, the reverse bias is kept at a

specified low-level VOS to minimize the impact of the dark current.

As the PD current increases, the reverse bias increases accordingly

to minimize the impact of the series resistance. To use this function,

the cathode of the PD should be connected to the PDB pin.

Figure 30. Adaptive PDB Principle of Operation

The ADL5308 PDB can be optimized for specific PDs through the

I2C interface. The reverse bias level at low input currents VOS, the

transresistance RT, that is, the change in bias voltage for a given

change in bias current, and the threshold current ITH above which

the transresistance takes effect can all be adjusted through the I2C

interface.

For input currents above ITH, ringing could be observed on the

PDB pin due to the positive feedback of the adaptive PD bias

via the PD capacitance. Typically, the frequency of the ringing is

around 100MHz and doesn’t propagate noticeably to the VLOG

output because it is attenuated strongly since its bandwidth is much

lower. For PD’s with capacitance below 3 pF, no sustained ringing

(oscillation) is observed even at cold temperatures. It is possible

however that for PD’s with larger capacitance sustained ringing

could occur. In that case, it is recommended to connect a snubber

network consisting of a 10 Ω resistor in series with a 220 pF capac-

itor between the PDB pin and ground to reduce ringing. Since the

ringing depends on the PD’s capacitance vs. its reverse voltage,

series resistance and PCB layout, it is good practice to measure the

ringing on the PDB pin using a pulsed optical source that generates

an input current well above ITH to make sure the ringing is not

excessive. If needed, the 220 pF capacitor can be scaled up or the

PDBG register contents, which sets the transresistance, be scaled

down.

RT can be enabled or disabled, that is, effectively set to zero,

through the PDBG_FIX flag in REG_14 (see Table 6). When dis-

abled (PDBG_FIX=1), the reverse bias voltage across the diode

does not change with the diode current but remains constant over

the entire input current range. When enabled (PDBG_FIX=1), the

PDBG bit field adjusts the transresistance value in 11.72 Ω steps.

An expression for RT in terms of the REG_14 register bit fields is

given in Equation 11. Note that setting either PDBG_FIX = 1 or

PDBG = 0 disables the transresistance.

RT=11.72× 1−PDBG_FIX ×PDBG (11)

The threshold current ITH above which the transresistance RT be-

comes effective is controlled by PDBG and IDZ (dead-zone current)

in REG_15. It can be expressed as:

ITH=51μA× 79×IDZ −1

PDBG× 1−PDBG_FIX

(12)

The smallest, (minimum functional value for IDZ is 1) value for ITH is

obtained for IDZ = 1 and PDBG = 63, resulting in ITH = 63 µA and

goes infinite for PDBG_FIX = 1.

The initial bias voltage, or offset voltage between the PDB pin and

INP pin below ITH can be adjusted using registers REG_15 and

REG_19. Additionally, it is dependent on PDBG and PDBG_FIX. Bit

field IPDB in register REG_15 provides a coarse adjustment in 30

mV steps. Adding to this is a fine adjustment in 3 mV steps OS in

REG_19. The contribution of PDBG in REG_14 is dependent on the

state of the PDBG_FIX flag. The total nominal reverse PDB voltage

in (mV) can be expressed as:

VPDB −VINP =30×IPDB+3× OS−8

+93.75×PDBG×PDBG_FIX

(13)

Note that |VPDB − VINP| is minimized in the factory at low input

current for IPDB = 0 and PDBG_FIX = 0 by trimming OS register

and is therefore not necessarily 0 mV for OS = 8.

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