ADL5308ACCZ-R7 datasheet(16/22 Pages) AD

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Data Sheet

ADL5308

APPLICATIONS INFORMATION

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Rev. 0 | 16 of 22

Figure 35. Logarithmic Output Response vs. Time for IINP = 220 µA to 10 nA

Transition

A proprietary PD is used as an input current source for this

measurement, and it is believed that the response time for the

high-to-low current transition is limited by the PD itself, not by the

ADL5308. The 10% to 90% fall-time response time is about 2.4 µs

and the settling time within 2 dB (1 dB optical power) is about 3.5

µs.

CMP, CREF, and HYST Interface

The logarithmic output VLOG is compared to a voltage refer-

ence level using a built-in comparator. The reference voltage,

CREF_DAC, is controlled by an internal 7-bit DAC through I2C

(range 30.6 mV to 1.93 V in 7.4 mV step). When the VLOG

exceeds the CREF_DAC voltage, the comparator output (CMP)

goes to logic low.

The HYST pin voltage sets the hysteresis window, which also

depends on the internal CREF_DAC value, see Figure 29.

Note that the CREF pin is a monitor point to measure the

CREF_DAC output, use a 10 MΩ digital multimeter (DMM). If the

comparator is not used, then disable the COMP_EN register.

Figure 36. Simplified Comparator Interface for CREF_DAC > 0

PDB Interface

The PDB interface pin is shown in Figure 37. The purpose of this

pin is to generate a bias voltage to be used with PDs.

In an optical system, the PD produces an output current proportion-

al to the optical input power. This results in an output dynamic

range that is twice (in dB) the optical input power dynamic range,

and can be quite high. At low input power, the input current can be

very small, on the order of pA. Here it is necessary to minimize the

dark current leakage of the PD by keeping the voltage drop across

the diode as small as possible. At higher input powers, the PD

current can be relatively large (up to 10s of mA). This photocurrent,

impressed on the internal series resistance of the diode, results in

an increasing voltage drop for increasing optical power.

To address the dark current issue, the ADL5308 provides a PDB

that keeps the PD's cathode-to-anode voltage close to zero for

low input current, therefore reducing any dark currents. For higher

current operation, the PDB Interface tracks the input current and

produces an output voltage directly proportional to the input current,

with the gain adjustable by the PDBG register. The transresistance

can be disabled by asserting the PDBG_FIX bit or setting PDBG =

0. The PDB output voltage is limited by the power supply voltage,

VCC.

Figure 37. Simplified Schematic of PDB Interface

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