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ADL5308ACCZ-R7 Scheda tecnica(PDF) 19 Page - Analog Devices

Il numero della parte ADL5308ACCZ-R7
Spiegazioni elettronici  Fast Response 188 dB Range (10 pA to 25 mA) Logarithmic Converter
PDF  22 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADL5308ACCZ-R7 Scheda tecnica(HTML) 19 Page - Analog Devices

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Data Sheet
ADL5308
SERIAL-PORT INTERFACE
analog.com
Rev. 0 | 19 of 22
REGISTER SUMMARY
Table 6. ADL5308 I2C Register Details1
Address
Name
Bits
Field Name
Description
Default
Access
0x00
REG_00
0
SOFTRESET
Writing 1 to this bit resets all registers to their default
values.
0x00
R/W
0x01
REG_01
[7:0]
CHIP_ID
ID for the ADL5308.
0x6D
R
0x10
REG_10
[3:0]
IMAX
Maximum PDB output current.
0x06
R/W
0x11
REG_11
[6:0]
IPT
IREF PTAT current.
0x37
R/W
0x12
REG_12
[6:0]
ICT
IREF CTAT current.
0x49
R/W
0x13
REG_13
4
IREFDIS
Reference current disable (used for ratio measure-
ments).
0x0A
R/W
[3:0]
IREF
Reference current adjust.
0x14
REG_14
6
PDBG_FIX
PDB transresistance is disabled (effectively set to zero) if
this bit is set, making the PDB voltage constant vs. input
current.
0x18
R/W
[5:0]
PDBG
PDB transresistance control when PDBG_FIX is not set,
PDB voltage control in 93.75 mV steps when PDBG_FIX
is set.
0x15
REG_15
[7:4]
IDZ
PDB transresistance threshold control.
0x70
R/W
[3:0]
IPDB
Controls the PDB voltage at in 30 mV steps.
0x18
REG_18
[5:0]
MTEMP
Slope temperature drift control.
0x00
R/W
0x19
REG_19
[7:4]
OS
VPDB − VINP offset control in 3 mV steps.
0x74
R/W
[3:0]
CF
Low input current bandwidth (CF = capacitor feedback).
0x1A
REG_1A
[5:3]
PT
Band-gap PTAT control.
0x51
R/W
[2:0]
ZT
Band-gap ZTAT control.
0x1B
REG_1B
[7:0]
LG
Logarithmic slope adjust.
0x07
R/W
0x1C
REG_1C
[2:0]
VPED
Starting voltage adjust.
0x03
R/W
0x1D
REG_1D
[5:0]
CREF_DAC
Comparator reference level generated by internal DAC if
CREF_DAC is not 0 and the external reference level for
CREF_DAC = 0.
0x00
R/W
0x20
REG_20
0
COMP_EN
Comparator enable. Enabled when COMP_EN = 1, disa-
bled when COMP_EN = 0.
0x01
R/W
0x48
REG_48
0
NVM_BYPASS2
Nonvolatile memory (NVM) bypass.
0x00
R
0x70
REG_70_TRIMMED_10
[3:0]
IMAX_RDBK
Readback register for the trimmed IMAX value of
REG_10.
0x0X
R
0x71
REG_71_TRIMMED_11
[6:0]
IPT_RDBK
Readback register for the trimmed IPT value of REG_11. 0xXX
R
0x72
REG_72_TRIMMED_12
[6:0]
ICT_RDBK
Readback register for the trimmed ICT value of REG_12. 0xXX
R
0x73
REG_73_TRIMMED_13
4
IREFDIS_RDBK
Readback register for the trimmed IREFDIS value of
REG_13.
0x0X
R
[3:0]
IREF_RDBK
Readback register for the trimmed IREF value of
REG_13.
0x74
REG_74_TRIMMED_14
6
PDBG_FIX_RDBK
Readback register for the trimmed PDBG_FIX value of
REG_14.
0x18
R
[5:0]
PDBG_RDBK
Readback register for the trimmed PDBG value of
REG_14.
0x75
REG_75_TRIMMED_15
[7:4]
IDZ_RDBK
Readback register for the trimmed IDZ value of REG_15. 0x10
R



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