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HMC1061LC5TR-R5 Scheda tecnica(PDF) 3 Page - Analog Devices |
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HMC1061LC5TR-R5 Scheda tecnica(HTML) 3 Page - Analog Devices |
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3 / 18 page  Data Sheet HMC1061LC5 Rev. B | Page 3 of 18 SPECIFICATIONS ELECTRICAL SPECIFICATIONS TA = 25°C. Table 1. Parameter Test Conditions/Comments Test Level1 Min Typ Max Unit ANALOG INPUTS (INP, INN) Differential Full-Scale Range Full-scale input for linearity test I 1 V p-p Input Resistance Each lead to ground III 50 Ω Return Loss 0 GHz to 12 GHz III 12.5 dB 12 GHz to 18 GHz III 6 dB Input Common-Mode Voltage III −0.1 0 +0.1 V CLOCK INPUTS (CLKAP, CLKAN, CLKBP, CLKBN) DC Differential Clock Voltage High III 20 40 2000 mV Low III −2000 −40 −20 mV Amplitude (Sinusoidal Input) Per port II −6 0 +10 dBm Input Common-Mode Voltage III −0.5 0 +0.5 V Clock Slew Rate Recommended for best linearity III 2 to 4 V/ns Return Loss 0 GHz to 3 GHz III 18 dB 3 GHz to 6 GHz III 11 dB Input Resistance Each lead to ground III 50 Ω ANALOG OUTPUTS (OUTP, OUTN) Differential Full-Scale Range IV 1 V p-p Common-Mode Output Voltage IV 0 V Differential Output Voltage I −50 0 +50 mV Output Impedance Per port III 50 Ω Return Loss 0 GHz to 5 GHz III 14 dB TRACK MODE DYNAMICS Baseband Gain I −2.5 0 +1 dB Track Mode Bandwidth At 1 V p-p input IV 5.1 GHz HOLD MODE DYNAMICS Sampling Bandwidth At −3 dB gain, 1 V p-p input level III 18 GHz Differential Droop Rate (Linear Component) I −1.4 %/ns Differential Droop Rate Magnitude (Fixed Component) I 4 mV/ns Feedthrough Rejection At 3 GHz III ≥65 dB Integrated Noise2 500 MHz clock frequency III 1.45 mV rms Maximum Hold Time First Rank III 2 ns Second Rank III 2 ns Total Maximum Effective Hold Time III 4 ns Single Tone at 0.995 GHz Full-scale input (1 V p-p)3 III Total Harmonic Distortion (THD) −54 dB Spurious-Free Dynamic Range (SFDR) 54 dB Single Tone at 1.995 GHz Full-scale input (1 V p-p)3 III THD −55 dB SFDR 55 dB Single Tone at 2.995 GHz Full-scale input (1 V p-p)3 III THD −54 dB SFDR 54 dB Single Tone at 3.995 GHz Full-scale input (1 V p-p)3 I THD −55 dB SFDR 56 dB |
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