HMC1061LC5TR-R5 datasheet(13/18 Pages) AD

13 / 18 page

Data Sheet

HMC1061LC5

Rev. B | Page 13 of 18

THEORY OF OPERATION

The HMC1061LC5 ultra wideband, dual rank, track-and-hold

amplifier is optimized for use in microwave data conversion

applications requiring maximum sampling bandwidth, high

linearity over a wide bandwidth, and low noise. A key

application of this device is front-end sampling for high speed

ADCs to enhance their input bandwidth and/or high frequency

linearity. Although several high speed ADCs offer enhanced

sample rates, few of them offer input bandwidth beyond a few

GHz. In addition, maintenance of good sampling linearity at

frequencies beyond the ultrahigh frequency (UHF) band is

technologically challenging and most ADC converters suffer

rapidly degraded linearity above a 1 GHz or 2 GHz signal

frequency. The HMC1061LC5 addresses these limitations with

a 18 GHz input bandwidth and excellent broadband linearity.

After sampling takes place within the track-and-hold amplifier,

the low bandwidth held output waveform can be processed by

an ADC with substantially reduced bandwidth. In addition,

ADC converter linearity performance limitations at high input

frequencies are also mitigated because the settled waveform is

processed with the optimal baseband linearity of the ADC

converter.

The dual rank track-and-hold amplifier is formed from two

cascaded, single rank track-and-hold amplifier that are clocked

180 degrees out of phase such that, while the master Track-and-

Hold 1 device (TH1) is holding, the slave Track-and-Hold 2

device (TH2) is tracking, and vice versa. The resulting output

waveform consists of two time segments. The first segment

consists of the TH1 hold mode as seen through TH2 track

mode transfer function. At the beginning of the second time

segment, TH2 samples the held TH1 waveform and then

continues to hold that value while TH1 switches back to track

mode and reacquires and tracks the input waveform. The

resulting output waveform provides a held sample value of

nearly one complete clock cycle, presenting the downstream

ADC with a constant, settled waveform with minimal high

frequency spectral content.

The device can be clocked in one of two ways, depending on the

voltage applied to the CLK_SELECT terminal. The device can

be configured such that the slave track-and-hold amplifier uses

an internal clock derived and buffered from the master clock

(Clock A). In this case, the CLK_SELECT terminal must be

grounded, the user provides Clock A, and the internal clock

driving the slave always operates at the same frequency as the

master, Clock A. Alternatively, the CLK_SELECT terminal can

be connected to the VEE supply, enabling external Clock B control

of the slave. In this mode, users must supply both Clock A and

Clock B, but have the option of operating the slave at the same

frequency or even a different frequency than the master. This

mode is useful for decimation operations (where Clock B is a

submultiple of the master clock) or other more complex clocking

schemes. In all cases, the maximum hold time limits shown in

Table 1 must be followed.

ESD

On-chip ESD protection networks are incorporated on the

terminals, but the RF or microwave compatible interfaces

provide minimal protection and ESD precautions must be used.

POWER SUPPLY SEQUENCING

The recommended power supply start-up sequence is VCCOB,

VCCOFx, VCCTH, VCCCLK, and VEE/VEE CLKx if biased from

independent supplies. VCCOB, VCCOFx, VCCTHx, and VCCCLKx

can be connected to one 2 V supply if desired.

INPUT SIGNAL DRIVE

For best results, the inputs must be driven differentially. The

input can be driven single-ended, but the linearity of the device

degrades. The unused input must be terminated in 50 Ω when

driving the device single-ended.

CLOCK INPUT

The first rank device is in track mode when CLKAP – CLKAN

is high and it is in hold mode when CLKAP – CLKAN is low.

The second rank device has an opposite polarity clock. It is in

track mode when CLKBP − CLKBN is low. The clock inputs

must be driven differentially if possible. The clock inputs can be

driven single-ended if desired, but the single-ended amplitude

and slew rate must be similar to the full differential amplitude

and slew rate recommended for differential drive. The unused

input must be terminated to 50 Ω.

The track-and-hold mode linearity of the device varies somewhat

with clock power at lower clock frequencies; this results from a

weak dependence of the linearity on clock zero crossing slew rate

for slew rates beneath a critical value. For optimal linearity, a

clock zero-crossing slew rate of roughly 2 V/ns to 4 V/ns (per

clock input) or more is recommended. For sinusoidal clock inputs,

4 V/ns corresponds to a sinusoidal clock power per differential

half circuit input of −6 dBm at 4 GHz, 0 dBm at 2 GHz, and 6 dBm

at 1 GHz. Regardless of the clock frequency, a minimum clock

amplitude of −6 dBm is recommended (per differential half circuit

input).

OUTPUTS

The outputs must be sensed differentially for the cleanest output

waveforms. The output impedance is 50 Ω resistive returned to

the VCCOB supply. The output stage is designed to drive 50 Ω

terminated to ground on each differential half circuit output.

The HMC1061LC5 offers a true ground referenced common-

mode output that is typically within ±50 mV of ground; however,

it is possible to adjust the VCCOB power supply slightly to fine

tune the output common-mode voltage level to precisely 0 V if

desired.

HMC1061LC5TR-R5 Scheda tecnica(PDF) 13 Page - Analog Devices

HMC1061LC5TR-R5 Scheda tecnica(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Scheda tecnica Scarica

Link URL