Data Sheet

HMC1061LC5

Rev. B | Page 5 of 18

Parameter

Test Conditions/Comments

Test Level1

Min

Typ

Max

Unit

Single Tone at 13.995 GHz

Half full-scale input (0.5 V p-p) 3

III

THD

−33

dB

SFDR

34

dB

Single Tone at 15.995 GHz

Half full-scale input (0.5 V p-p) 3

III

THD

−36

dB

SFDR

38

dB

Single Tone at 17.995 GHz

Half full-scale input (0.5 V p-p) 3

III

THD

−36

dB

SFDR

37

dB

TRACK TO HOLD AND HOLD TO TRACK SWITCHING

Aperture Delay

Simulated value

−6

ps

Random Aperture Jitter

Full-scale input at 1 GHz3

III

<70

fs

Differential Pedestal (Linear Component)

First Rank

1 GHz clock frequency, 6 dBm clock

power

III

−1.0

%

Second Rank

1 GHz clock frequency, 6 dBm clock

power

III

0.15

%

Differential Pedestal Magnitude (Fixed

Component)

First Rank

III

2.8

mV

Second Rank

III

1.6

mV

Clock Frequency

At 50% duty cycle

III

250

4000

MHz

Clock Buffer Pipeline Delay

Simulated value

35

ps

Acquisition Time to 1 mV

Simulated value

132

ps

Settling Time to 1 mV

Simulated value

135

ps

Output Buffer Delay (from Second Rank Hold

Node to Output)

Simulated value

43

ps

POWER SUPPLY REQUIREMENTS

VCCTH Voltage (VCCTH1 and VCCTH2)

1.9

2

2.1

V

VCCTH Current (Sum of VCCTH1 and VccTH2)

I

140

mA

VCCOF Voltage (VCCOF1 and VCC OF2)

1.9

2

2.1

V

VCCOF Current (Sum of VCCOF1 and VCCOF2)

I

47

mA

VCCOB Voltage

1.9

2

2.1

V

VCCOB Current

I

74

mA

VCCCLK Voltage (VCCCLK1 and VCCCLK2)

1.9

2

2.1

V

VCCCLK Current (Sum of VCCCLK1 and VCCCLK2)

I

64

mA

VEE Voltage (VEECLK1, VEECLK2, VEE)

−5

−4.75

−4.5

V

(VEE + VEECLK) Current

I

−357

mA

Power Consumption

I

2.34

W

1

See Table 3.

2

The noise bandwidth is limited by an output amplifier bandwidth of ~7 GHz.

3

1 GSPS clock, clock power = 6 dBm per input terminal.