HMC1061LC5TR-R5 datasheet(15/18 Pages) AD

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Data Sheet

HMC1061LC5

Rev. B | Page 15 of 18

product measurement avoids excessive envelope correction

error by maintaining all beat products within the 4 dB bandwidth

of the sinc function, where the envelope response is stable and

easily modeled.

Independent and accurate measurement of linearity in a track-

and-hold amplifier waveform (without a downstream ADC to

sample a single point on the held waveform) is challenging at

these low nonlinearity levels. This challenge is due to the waveform

transitions and/or small glitches that can impact the measured

spectrum during direct spectrum analyzer measurements of the

output waveform (without sampling). These measurement arti-

facts are worst case at high clock frequencies where a significant

fraction of the waveform duration is consumed by transients. It is

believed that these measurement artifacts at high clock frequencies

contribute to the linearity ripple, which is seen in the plots at

higher clock rates. The true linearity is likely represented by the

average through these curve variations.

For the same reasons described previously, the linearity charac-

terization of the track-and-hold amplifier waveform via direct

spectrum analysis tends to represent a worst case scenario relative

to the true linearity obtained by sampling one point on the held

waveform as would be obtained during track-and-hold amplifier

ADC measurements. This is supported by our track-and-hold

amplifier ADC combination measurements documented in this

data sheet and in the AN-1472 Application Note, the AN-1474

Application Note, and the AnalogDialogue article, Radically

Extending Bandwidth to Crush the X-Band Frequencies Using a

Track-and-Hold Sampling Amplifier and RF ADC, which discuss

substantially better linearity, particularly at low signal

frequencies. The measured linearity presented from direct

spectrum analysis of the entire track-and-hold amplifier waveform

is believed to represent a worst case indication of the true track-

and-hold linearity. The AN-1472 Application Note is for the

single rank version of the track-and-hold amplifier, the HMC661,

upon which the HMC1061LC5 dual rank design is based.

This effect is shown by the track-and-hold amplifier ADC

assembly performance data in Figure 16. Figure 16 shows the

typical sampling transfer function and linearity obtained by

using the HMC1061LC5 as a front-end sampler for a high

speed, 12-bit ADC as derived from a breadboard setup using the

HMC1061LC5 evaluation board and the ADC reference board

operating at 1 GSPS sample rate.

The track-and-hold amplifier is driven with a differentially leveled

input signal from 1 GHz to 18 GHz at 1.5 dB full-scale referenced

to the track-and-hold amplifier full-scale level of 1 V p-p differ-

ential, as shown in Figure 16. The track-and-hold amplifier

baseband gain of ~0.5 dB, combined with the signal loss in the

input traces of the ADC evaluation board (1 dB), results in a

1 dBFS input level to the converter, relative to its 0.8 V p-p

differential full-scale level. As the data shows in Figure 16, the

3 dB bandwidth of the composite sampling process is 18 GHz as

established by the front-end track-and-hold amplifier sampler.

Inspection of the second and third-order product levels show

that the linearity performance of the composite track-and-hold

amplifier ADC assembly is actually better than the performance

measured for the track-and-hold amplifier alone with direct

spectrum analyzer measurement of the track-and-hold amplifier

waveform. This is particularly true at low frequencies where the

SFDR is 61 dB to 62 dB vs. the 57 dB that is expected by third-

order product limitations at 1.5 dBFS track-and-hold amplifier

levels. These differences are due to the additional measurement

artifacts introduced by the track-and-hold waveform transitions in

direct spectrum analyzer measurement. For this reason, the

linearity performance of the track-and-hold amplifier ADC

assembly tends to be a better indicator of the true track-and-

hold linearity as long as the ADC has a low frequency baseband

SFDR several dB higher than the track-and-hold amplifier, such

that the track-and-hold amplifier nonlinearity dominates. Due

to the relatively high track-and-hold amplifier linearity, typically

the condition of track-and-hold amplifier nonlinearity domination

can only be met by ADCs with 12 bits or more of resolution.

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